PG Diploma in VLSI Design &ASIC Verification
Durations – 500 Hrs.
Core Programming Fundamentals
- Digital Hardware Familiarization
Core Programming Fundamentals
- Mastering in C++
VLSI Design
- RTL Coding with Verilog
- Digital Circuit Design with Different Modeling Styles
- On-Chip Protocol Design
- FPGA Programming
SPECIALIZATIONS
VLSI Verification using SystemVerilog
- Design and Verification using SystemVerilog
- OOPs in SystemVerilog
- Randomization & Constraints
- Functional Coverage
- Testbench Development
- Static Timing Analysis
- ASIC Timing
ASIC Verification using UVM
- Verification Methodology
- Protocol Verification
- Python Scripting Methodology
Technology Platform
- Xilinx Vivado
- Artix-7 FPGA Board
- Yosys
- QuestaSim / EDA Playground
- Zynq SoC Board
- OpenTimer
IndustryJobRoles:
- RTL Design Engineer
- ASIC Design Engineer
- Verification Engineer (SystemVerilog / UVM)
- FPGA Design Engineer
- Static Timing Analysis (STA) Engineer
- Embedded / VLSI Software Engineer
