Advanced Diploma in VLSI Design & Verification
Durations – 300 Hrs. -Offline
Modules
Core Engineering
- Digital Hardware Familiarization
- Digital Electronics, Logical Circuit Design
- Timing Analysis
-
- Mastering OOP using C++
- Linux Basic Commands
-
- RTL Coding with Verilog
- Digital Circuits Design with Different Modeling Styles
- On-Chip Protocols Design
- FPGA Programming SPECIALIZATIONS
- Design and Verification Using SystemVerilog
- OOPs in SystemVerilog
- Randomization & Constraints
- Functional Coverage
- Test Bench Development
Project stream:
Core Programming
-
- Application development based on Data Structure (Eg: Multi Client Chat Application, memory Leak Detection tool kit, E-Commerce cart simulator)
-
- Design and Simulation of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation and Verification of Digital Controllers, ALU Cores and Protocols such as UART, SPI, I2C, AXI4 on FPGA Board
- SV Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
Platform:
- XILINX VIVADO
- Questasim / EDA Playground
- Artix7 FPGA Board / ZYNQ SOC Board
Experiential Project Based Learning
- A Prototype Digital System Design using RTL Modeling
- FPGA Deployment, and SystemVerilog-Based Verification
Core Engineering
Digital Hardware Familiarization – 40 hrs. – 7 Days – 1 Weeks ( Online / Recording )
Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics
Diodes, Rectifiers, Zener & Clamping Circuits
BJTs and MOSFETs (Switching & Amplification)
Operational Amplifiers (Op-Amps), Filters
Digital Electronics & Logic Design: Number Systems & Boolean Algebra
Logic Gates, Multiplexers
Comparators, Encoders/Decoders
Flip-Flops, Counters, Shift Registers,
FSMs, Timing Analysis Basics
Assessment – Module Test – MCQ, Theory
Technical Mock
Core Programming Fundamentals
Mastering OOP using C++ & Competitive problem solving – 60 hrs. – 10 Days – 2 Weeks
Basic input / output: cin, cout, >> and << operators, endl, setw
Understanding namespace Introduction to Object-Oriented Programming
Classes and objects, Encapsulation, Data hiding, abstraction
Access Specifiers – Private and Protected, This pointer
Constructors and Destructors
Friend functions and operator overloading
Inheritance, Run time polymorphism, Exception Handling, Lambda Expression
Smart Pointers, Templates, STL Algorithms, STL Container Classes
Iterators
Project- Intermediate project & Demo
Assessment – Module Test – MCQ, Theory
Technical Mock
| Linux System Programming using C – 30 hrs – 5 Days – 1 Weeks | ||
|---|---|---|
| Linux Shell Commands | Manipulating files and directories | Manipulating data, Find and Grep |
| Assessment – Module Test – MCQ, Theory | Technical Mock | |
| VLSI Design | ||
|---|---|---|
| RTL Coding with Verilog – 60 hrs. – 10 Days – 2 Weeks | ||
| INTRODUCTION TO VLSI: Fundamentals of VLSI | Design Methodology | Verilog data types, Verilog Operators |
| GATE LEVEL MODELING: Gate Instantiate | Design RTL From logic Diagram, Logic Gate primitive | Delay in Gate level Design |
| DATA FLOW MODELING: Operators in Data Flow | Continuous Assignment (assign statement) | Boolean Equations Representation |
| Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator? 🙂 | Procedural continuous Assignment Statement |
| Procedural vs Continuous Assignment | Parameterized Data Flow Design Delay Modeling in Data Flow |
Case Studies / Examples (ALU, Adders, MUX, Encoders) |
| BEHAVIORAL MODELING: Structured procedural Statement: Always Statement, Procedural Statement | Blocking Statement, Non-Blocking statement | Timing Control Statement: Delay based timing control; Event Based timing control |
| Conditional Statement: If else statement, case statement: casex, casez | Loop: While, do while, for, for each, forever, repeat. | Block statement, Sequential block, Parallel Block |
| De-assign Statement, force statement, Release statement | DESIGN OF DIGITAL CIRCUITS FSM: Mealy machine, Moore machine |
Flip-flops , Counters, Shift Registers |
| All combinational and sequential circuits using Verilog, CRC checking, PWM | DESIGN OF DIGITAL CIRCUITS: FSM: Mealy machine, Moore machine | Useful Of Modeling Technique, All combinational and sequential circuit using Verilog |
| Project- Advanced project & Demo | Assessment – Module Test – MCQ, Theory | Technical Mock |
| On-Chip Protocols Design – 20 hrs. – 3 Days – 0.5 week | ||
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol , I2C (Inter Integrated Circuit) protocol | AXI4 (Advanced extensible Interface 4) protocol |
| FPGA Programming – 36 hrs. – 6 Days – 1Weeks | ||
| Introduction to FPGA , FPGA Architecture | CLB, I/O blocks, Interconnects | CPLD, FPGA, FPGA Working, Design Flow, Tool Understanding |
| working Designing basic FPGS example (Adders, Subtractors, Counter) | Implementation of all the combinational circuits on FPGA | Implementation of Flip-flops on FPGA |
| Implementation of Counters- up counter, down counter, up-down counter, mod-counter, Johnson counter, ring counter | Realization of Shift Registers Demonstration of a Project on FPGA |
Realization of FSM: Mealy machine, Moore machine, Designing with VIO and ILA |
| Assessment – Module Test – MCQ, Theory | Technical Mock | |
| Specializations | ||
| VLSI Verification using System Verilog | ||
| Design and Verification using System Verilog – 80 hrs. – 15 Days – 3 weeks | ||
| Introduction of System Verilog, Need of system Verilog | Environment of Verification | Data types - 2state, 4 state, enum, string, structure, union, class |
| Array- Fixed array- packed and unpacked array | Dynamic Array, Associative array | Queues |
| Process: - Fork-join, Fork-join any, Fork- join none, Wait-fork | OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation | Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage. |
| Explanation of assertion with example | Explanation of coverage with example | Working on verification environment |
| Project- Advanced project & Demo | Assessment – Module Test – MCQ, Theory | Technical Mock |
