Advanced RTL Designs with Protocols
Duration: 4 Weeks
Project Training – Offline / Online
Program Summary:
- Introduction to VLSI design flow and Verilog HDL fundamentals.
- Hands-on learning of gate-level, dataflow, and behavioral modeling.
- Design of combinational and sequential digital circuits using Verilog.
- Implementation of UART, SPI, I²C, and AXI communication protocols.
- System-level integration of multiple RTL modules.
- Project development and student presentations.
Program Outcomes:
- Model digital systems using Verilog across various abstraction levels
- Simulate and debug designs using professional EDA tools
- Design synthesizable communication protocol modules
- Integrate functional blocks into complete digital systems
- Demonstrate and present working RTL-based projects.
Project stream:
- ALU & Code Converters (Digital system design)
- FSM-Based Controllers (Traffic light, vending machine, password lock)
- Sequential Logic Projects (Counters, shift registers, clock dividers)
- Protocol Implementations (UART, SPI, I2C, AXI4)
- System Integration Projects (Memory interface, CRC checker, mini SoC
Platform:
- XILINX VIVADO
- Questasim / EDA Playground
| Days 1–15: Theory + Simulation Labs | ||
| Day | Topics | Hands-on Activities |
|---|---|---|
| Day 1 | Introduction to Digital Design & RTL | Review of combinational & sequential logic |
| Day 2 | Verilog HDL Basics | Verilog syntax, modules, testbenches |
| Day 3 | RTL Design Methodology | Design abstraction levels, FSM design |
| Day 4 | Combinational Logic Design | ALU, MUX, Encoder, Decoder in Verilog |
| Day 5 | Sequential Logic Design | Flip-flops, Counters, Registers |
| Day 6 | FSM-Based Design | Mealy/Moore Machines, vending machine |
| Day 7 | Synthesis & Simulation Tools | Using ModelSim / Vivado / Synplify |
| Day 8 | Advanced Verilog Constructs | Generate, define, parameterized modules |
| Day 9 | Bus Protocols Overview | Introduction to AMBA, I2C, SPI, UART |
| Day 10 | UART Protocol Deep Dive | UART Transmitter/Receiver RTL design |
| Day 11 | SPI Protocol Deep Dive | SPI Master/Slave RTL design |
| Day 12 | I2C Protocol Deep Dive | Bit-banging I2C Master design |
| Day 13 | AMBA AHB Protocol | Basic AHB-lite |
| Day 14 | APB Protocol | APB read-write models |
| Day 15 | AXI Protocol | AXI-Lite |
| Days 16–20: Final RTL Project | ||
| Day 16 | Project Kickoff | Requirement analysis, RTL block diagram |
| Day 17 | RTL Coding | Module-level implementation |
| Day 18 | Functional Simulation | Testbench creation & waveform analysis |
| Day 19 | Synthesis & Reporting | Timing, area reports |
| Day 20 | Final Demo & Report Submission | Simulation demo, oral presentation, feedback |
