VLSI Design & ASIC Verification

Program Summary

VLSI Design & ASIC Verification
- Digital logic design & RTL coding in Verilog
- SystemVerilog for design and verification
- UVM-based verification methodology
- On-chip protocol design & verification (UART, SPI, I2C, AXI4)
- Static Timing Analysis (STA) fundamentals
- Synthesis and digital physical design flow
- FPGA implementation and scripting automation (Python, TCL)
Industry-Demand Add-Ons (woven into labs & capstone)
- RTL Linting & CDC Awareness — clock domain crossing checks
- Logic Equivalence Checking — LEC / Formality basics
- Low-Power Design — UPF basics, clock gating awareness
- SDC Constraints & Timing Exceptions — multi-cycle & false paths
- Python & TCL Scripting — EDA automation & report parsing
- EDA Tool Fluency — Vivado, Questasim, Cadence Innovus, Synopsys IC Compiler II
- ECO Flow & Tape-out Basics — signoff awareness
- Git for Design Teams — version control workflows
Capstone Project (5 Days)
- Custom protocol IP design, verification and FPGA implementation
- Synthesis, STA and basic physical design checks
- Industry-style documentation, demo and mock interview

Software
- Xilinx Vivado Suite
- Questasim / EDA Playground
- Yosys, OpenTimer
Hardware
- Artix-7 FPGA Board
- Zynq SoC Board
- Laptop/Desktop (Minimum 8 GB RAM)

Free Access to Cranes Digital Academy
- A Self Learning Platform
- Turning Classroom Learning into Career-Ready Skills
- CDA connects learning → practice → assessment → projects → placement
- Ensures student learning activity turns into measurable career readiness
Placement Assistance
- Placement will be extended to Top 5 performing students per batch
- Merit-based approach
- Focused mentorship and Interview preparation