VLSI Design and System Verilog Verification
Pre-requisites
- Basics of Digital Electronics
- Knowledge of Logic Gates, Flip-Flops & FSM
- Basic understanding of Verilog / HDL concepts
Tools / Platform:
- SystemVerilog
- UVM
- QuestaSim / Xcelium / VCS
- EDA Playground
Take away
- Hands-on experience in UVM testbench development
- Verification of digital designs using SystemVerilog & UVM
- Understanding of functional coverage, assertions, and debugging
- Industry-ready verification skills and mini project experience
