Verification using UVM
Pre-requisites
- Digital Electronics fundamentals
- Verilog HDL basics
- Basic SystemVerilog knowledge
Tools / Platform:
- SystemVerilog
- UVM
- QuestaSim / Xcelium / VCS
- EDA Playground
Take away
- Hands-on experience in UVM testbench development
- Verification of digital designs using SystemVerilog & UVM
- Understanding of functional coverage, assertions, and debugging
- Industry-ready verification skills and mini project experience
