SoC Verification Using System Verilog with Industry Bus Protocols
Durations -20 days.
Program Structure
- RTL Designs Using Verilog/VHDL – Prerequisite
- OOPs Concepts of C++ Programming – Prerequisite
- System Verilog Essentials – 4 days
- System Verilog Basics & Data Types
- Procedural Blocks & RTL Constructs
- Interfaces, Modports & Assertions
- Verification-Oriented Features
- Verification of Serial Communication Protocols – 3 Days
- UART (Universal Asynchronous Receiver Transmitter)
- I2C (Inter Integrated Circuit)
- SPI (Serial Peripheral Interface)
- Verification of On-Chip Protocols – 3 Days
- AHB (Advanced High-performance Bus)
- APB (Advanced Peripheral Bus)
- AXI-4 (Advanced eXtensible Interface)
Projects: Stream
Program Outcomes
- Apply SystemVerilog fundamentals and verification-oriented features to develop structured, reusable, and synthesizable RTL and verification code.
- Design and implement SystemVerilog-based testbenches using procedural blocks, interfaces, modports, assertions, and object-oriented concepts.
- Verify serial communication protocols (UART, I2C, SPI) by creating protocol-compliant stimulus, checks, and coverage models.
- Verify on-chip bus protocols (AHB, APB, AXI-4) by validating functional correctness and protocol compliance using SystemVerilog methodologies.
Tools / Platform:
- EDA Playground
Assessment – MCQ’s, Module Test
System Verilog Essentials
Introduction to SystemVerilog vs Verilog
Data types: logic, bit, int, byte, shortint, longint
Packed vs unpacked arrays
Enumerations (enum) and structures (struct)
Type casting and typedef
Blocking vs non-blocking assignment
Procedural control statements (if, case, loops)
Tasks and functions
SystemVerilog interfaces and benefits
Modports and signal direction control
Introduction to SystemVerilog Assertions (SVA)
Immediate vs concurrent assertions
Object-Oriented Programming basics
Classes, objects, constructors
Randomization and constraints
Mailbox and event mechanisms
Testbench structure and reuse concepts
Testbench demonstration
Verification of Serial Communication Protocols
UART protocol overview and frame structure
SystemVerilog testbench architecture for UART
UART transmitter and receiver verification
| Functional coverage for UART transactions | I2C protocol overview and bus operation | SystemVerilog testbench with master/slave models |
| Verification of start/stop and addressing | Functional coverage for read/write transactions | SPI protocol overview and signal behavior |
| SystemVerilog testbench for SPI master/slave | Verification of SPI modes (CPOL/CPHA) | Functional coverage for full-duplex transfers |
| Verification of On-Chip Protocols | ||
|---|---|---|
| AHB protocol overview and signal behavior | SystemVerilog testbench architecture for AHB | Verification of address, data, and control phases |
| Functional coverage for AHB transfers and bursts | APB protocol overview and transfer states | SystemVerilog testbench for APB slave verification |
| Verification of read and write transactions | Functional coverage for APB access types | AXI-4 protocol overview and channel architecture |
| SystemVerilog testbench for AXI-4 master/slave | Verification of read/write and burst transactions | Functional coverage for AXI-4 channels and responses |
