VLSI Design and ASIC Verification-Tailored for Working Professionals
Duration: 6 Months (Online)
Eligibility: BE, B.Tech, ME, M.Tech
Intermediate
Advanced Diploma in VLSI Design & Verification
100% JOB Assured with Globally Accepted Certificate
Overview
If you are a working professional aiming to specialize in semiconductor design or verification, Cranes Varsity offers a career-focused Diploma in VLSI Design & ASIC Verification that fits perfectly into your busy schedule.
This program is delivered through flexible learning formats including
evening VLSI classes for professionals, and a fully accessible VLSI online training in Bangalore enabling you to learn without interrupting your work commitments.
As one of the leading VLSI training institute in Bangalore, Cranes Varsity has established a reputation for producing skilled VLSI engineers equipped with industry-relevant expertise.
Why Choose This Program?
This program is crafted for professionals who want to stay ahead in the competitive semiconductor and electronics industry. Whether you are looking to build a strong foundation in VLSI or aiming to advance your verification skills, this course offers:
- Evening VLSI Classes for Professionals – Flexible evening batches to accommodate your work schedule.
- VLSI Online Training in Bangalore – Learn from anywhere with our comprehensive online course platform.
- Best VLSI Courses Online – A well-structured curriculum recognized as one of the best for online VLSI learning.
- Industry-Relevant Curriculum – Focus on current VLSI design and verification tools and practices to make you job-ready.
- Hands-On Projects and Practical Labs – Gain real-world experience through practical assignments and projects.
Modules
- Digital Hardware Familiarization
- Digital Electronics and Logical Circuit Design
- Timing Analysis
- Mastering OOP using C++
- Linux Basic Commands
- RTL Coding with Verilog
- Digital Circuit Design using different Modeling Styles
- On-Chip Protocol Design
- FPGA Programming
- Prototype Digital System Design using RTL Modeling,
- FPGA Deployment, and SystemVerilog-Based Verification
SPECIALIZATIONS:
- Design and Verification using System Verilog
- OOPs in System Verilog
- Randomization & Constraints
- Functional Coverage
- Test bench development
- Duration Break up:
- Training – 55 Days (Excluding DHF)
- Project & Assessment & Technical Mock – 10 Days
Project stream:
- Core Programming
- Application development based on Data Structure (e.g., Multi Client Chat Application, Memory Leak Detection Toolkit, E-Commerce Cart Simulator)
- VLSI
- Design and Simulation of Digital Controller / CPU Core / Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation, and Verification of Digital Controllers, ALU Cores, and Protocols such as UART, SPI, I2C, AXI4 on FPGA Board
- SystemVerilog Verification of Digital Controller / CPU Core / Protocols such as UART, SPI, I2C, AXI4
Platform:
- XILINX VIVADO
- Questasim / EDA Playground
- Artix-7 FPGA Board / ZYNQ SoC Board
| Core Engineering | ||
|---|---|---|
| Digital Hardware Familiarization – 40 hrs. – 10 Days – 2 weeks | ||
| Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics | Diodes, Rectifiers, Zener & Clamping Circuits | BJTs and MOSFETs (Switching & Amplification |
| Operational Amplifiers (Op-Amps), Filters, Comparators | Digital Electronics & Logic Design: Number Systems & Boolean Algebra | Logic Gates, Multiplexers, Encoders/Decoders |
| Flip-Flops, Counters, Shift Registers, | FSMs | Timing Analysis |
| Core Programming Fundamentals | ||
|---|---|---|
| Mastering OOP using C++ & Competitive problem solving – 60 hrs. – 15 Days – 3 weeks | ||
| Master in C Programming: Simple C program structure | Literals, Constants, | Variables and Data types |
| Arrays | Sorting and searching | Strings |
| Mastering in C++ with OOPs concepts: Introduction to Object-Oriented Programming | Understanding OOP concepts | Objects |
| Understanding namespace | Classes | Basic input/output: cin, cout, endl |
| Abstraction | Encapsulation, | Access Specifiers – Private and Protected, |
| This pointer | Constructors and Destructors | Friends and operator overloading |
| This pointer | Constructors and Destructors | Friends and operator overloading |
| Inheritance | Run time polymorphism | Exception Handling |
| Lambda Expression | Smart Pointers Templates | STL Problem Solving using Hacker rank |
| VLSI Design | ||
|---|---|---|
| RTL Coding with Verilog – 60 hrs. – 15 Days – 3 weeks | ||
| INTRODUCTION TO VLSI: Fundamentals of VLSI | Design Methodology | Verilog data types, Verilog Operators |
| GATE LEVEL MODELING: Gate Instantiate | Design RTL From logic Diagram, Logic Gate primitive | Delay in Gate level Design |
| DATA FLOW MODELING: Operators in Data Flow | Continuous Assignment (assign statement) | Boolean Equations Representation |
| Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator? | Procedural continuous Assignment Statement |
| Procedural vs Continuous Assignment | Parameterized Data Flow Design Delay Modeling in Data Flow | Case Studies / Examples (ALU, Adders, MUX, Encoders) |
| BEHAVIORAL MODELING: Structured procedural Statement: Always Statement, Procedural Statement | Blocking Statement, Non-Blocking statement | Timing Control Statement: Delay based timing control; Event Based timing control |
| Conditional Statement: If else statement, case statement: casex, casez | Loop: While, do while, for, for each, forever, repeat. | Block statement; Sequential block, Parallel Block |
| De-assign Statement, force statement, Release statement | DESIGN OF DIGITAL CIRCUITS: FSM: Mealy machine, Moore machine | Flip-flops |
| Counters, Shift Registers | All combinational and sequential circuits using Verilog | CRC checking, PWM |
| DESIGN OF DIGITAL CIRCUITS: FSM: Mealy machine, Moore machine | Flip-flops | Counters, Shift Registers |
| Useful of Modeling Technique | All combinational and sequential circuit using Verilog | Delay Control Statement: Intra delay, inter delay, rise delay, fall delay |
| Procedural continuous, Assignment Statement | De-assign Statement, force statement, Release statement | CRC checking, PWM |
| On-Chip Protocols Design – 20 hrs. – 5 Days – 1 weeks | ||
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol | I2C (Inter Integrated Circuit) protocol |
| AXI4 (Advanced extensible Interface 4) protocol | ||
| FPGA Programming – 40 hrs. – 10 Days – 2 weeks | ||
|---|---|---|
| Introduction to FPGA | FPGA Architecture | CLB, I/O blocks, Interconnects |
| CPLD, FPGA, FPGA Working, | Design Flow, Tool Understanding | working Designing basic FPGS example (Adders, Subtractors, Counter) |
| Implementation of all the combinational circuits on FPGA | Implementation of Flip-flops on FPGA | Implementation of Counters- up counter, down counter, up-down counter, modcounter, Johnson counter, ring counter |
| Realization of Shift Registersv | Realization of FSM: Mealy machine, Moore machine, Designing with VIO and ILA | Demonstration of a Project on FPGA |
| Experiential Project based learning | ||
| Project: Digital design innovators: RTL to realization | ||
| Specializations | ||
|---|---|---|
| VLSI Verification using System Verilog | ||
| Design and Verification using System Verilog – 100 hrs. – 25 Days – 5 weeks | ||
| Introduction of System Verilog, Need of system Verilog | Environment of Verification | Data types-2satete, 4 state, enum ,string, structure, union, class |
| Array- Fixed array- packed and unpacked array | Dynamic Array, Associative array | Queues |
| Process: - Fork-join, Fork-join any, Fork- join none, Wait-fork | OOPS-Inheritance, Polymorphism, Data hiding, Encapsulation | Class- Deep copy, shallow copy,Overriding class, Coverage: Functional Coverage, Cross coverage. |
| Explanation of assertion with example | Explanation of coverage with example | Working on verification environment |
| ASIC Verification using UVM | ||
| Verification using UVM (Universal Verification Methodology) – 60 hrs. – 15 Days – 3 weeks | ||
| Introduction UVM: why UVM | UVM Objects: Base classes | UVM Macros, UVM Base Class Methods |
| UVM Phases, UVM Config DB, UVM Reporting Mechanism | UVM TLM Ports, Analysis, FIFO, UVM socket concept, UVM Callbacks | UVM test Bench Components and UVM test Benches. |
| On-Chip Protocols Verification – 20 hrs. – 5 Days – 1 weeks | ||
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol | I2C (Inter Integrated Circuit) protocol |
| AXI4 (Advanced eXtensible Interface 4)protocol | ||
| Experiential Project based learning | ||
| Project: Functional Verification: System Verilog to UVM | ||
| Python Scripting – 40 hrs. – 10 Days – 2 weeks | ||
| Python Fundamentals for Engineers | Data Structures and File Handling | Regular Expressions & Pattern Matching |
| Scripting for EDA Automation | Parsing Reports & Timing Files | Visualization & Reporting |
| Python for Verification & Testbenches | ||
| Timing Verification | ||
| Static Timing Analysis – 40 hrs. – 10 Days – 2 weeks | ||
| Introduction to RTL Linting and CDC | Introduction RTL Synthesis flow | Clocking and Clock domain/synchronization concepts |
| Timing Constraints Overview | Writing constraints | Submicron Process nodes and Technology libraries understanding |
| Synthesis process | Design optimization and netlist generation | Logic equivalence (LEC) /formality verification |
| Introduction to Static Timing Analysis,Terminologies in STA | Timing Fundamentals - Clock, reset,delays | Timing checks, Setup, Hold,Metastability etc |
| Understanding Timing Paths and types of timing paths | Timing checks | Timing Analysis for Combinational &Sequential Logic Circuits |
| Static Timing Analysis (STA) Flow understanding | Inputs and outputs of STA | Design rule violations |
| Timing exceptions | PVT corners and OCV | Understanding Setup and Usage of EDA tools relevant for Syntheis and STA |
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Testimonials
Positive: Communication, Professionalism, Quality, Value I Joined Cranes Varsity without any basic knowledge of programming or any interview-related knowledge. I enhanced my knowledge and skills by joining VLSI Course at Cranes Varsity. I got placed in Onward technologies during the 3rd month of my training as promised by the Cranes Varsity.
I am Nanditha N, have completed B.E. in the field of ECE in 2019, and had a wish to join the core company in the field of VLSI design, then I found Cranes Varsity as the best VLSI Training Institute for my dream to come true, a very best place and I got placed in Insemi Technology. I am very thankful for all the trainers who guided me with the best knowledge and skills and even the placement department who placed me in a very good company and for their great support. I suggest Cranes Varsity as the best training place to gain knowledge that helps us to build our careers.
I am Dileep Kumar T, completed my M.Tech in the stream of VLSI from Dr. AIT, Bangalore in 2019. I joined Cranes Varsity and did my professional course in VLSI Design which includes Verilog, system Verilog, FPGA, and uvm. I had a very good experience with Cranes Varsity, I got multiple opportunities from CranesVaristy. Finally, I got placed in DELOPT as a VLSI Design Engineer
I joined Cranes Varsity for VLSI Design & Verification Course. It is a very good training institute, they placed me in Radiant Semiconductor Pvt Ltd. Trainers were highly skilled and very supportive.
I am Veena Jogannavar, who completed a B.E in the field of ECE in 2020 from Sri Siddhartha Institute of Technology.I came to know about Cranes from my friend. I have undergone VLSI front-end design training and gained good knowledge in Digital electronics, Verilog, and System Verilog. I thank Cranes for providing opportunities for my career growth. At last, I got placed in DELOPT, Bangalore
I am Manavi BR.I have done my M.Tech in VLSI Course and Embedded system from BIT. My dream was to get place in a good core company. Cranes is a good place to learn programming and embedded systems. I got placed in Trident Infosol .I am very thankful to Cranes varsity
Mithun G
Nanditha N
Dileep Kumar T
Gaurav Pandey
Veena Jogannavar
Manavi BR
