Mastering VLSI Design & Verification
Durations -15 days.
Program Structure
VLSI Design
RTL Coding with Verilog
- VLSI fundamentals and design methodology
- Different styles of modeling
- Conditional and procedural statements, delay modeling
- Advanced RTL designs
Experiential Project Based Learning
Design and Verification using System Verilog
- System Verilog concepts, OOP
- Assertions, and coverage
- Complete verification environment design
Program Outcomes
- Apply gate, dataflow, and behavioral modeling to develop synthesizable RTL modules
- Implement FSM-based control logic using Moore or Mealy machine design principles
- Develop verification environments using SystemVerilog constructs (e.g., arrays, classes, assertions)
- Gain hands-on experience in designing, simulating, and verifying a real-world digital component
- Understand functional coverage planning, testbench development, and assertion-based verification, preparing for roles in ASIC/FPGA verification
AI Tools / Platform:
- Xilinx Vivado
- EDA Playground
Experiential Project Based Learning
- A Prototype Digital System Design using RTL Modeling and SystemVerilog-Based Verification
| VLSI Design | ||
|---|---|---|
| RTL Coding with Verilog | ||
| INTRODUCTION TO VLSI: Fundamentals of VLSI | Design Methodology | Verilog data types, Verilog Operators |
| GATE LEVEL MODELING: Gate Instantiate | Design RTL from Logic Diagram, Logic Gate primitive | Delay in Gate level Design |
| DATA FLOW MODELING: Operators in Data Flow | Continuous Assignment (assign statement) | Boolean Equations Representation |
| Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator? 🙂 | Procedural continuous Assignment Statement |
| Procedural vs Continuous Assignment | Parametered Data Flow Design Delay Modeling in Data Flow |
Case Studies / Examples (ALU, Adders, MUX, Encoders) |
| BEHAVIORAL MODELING: Structured procedural Statement: Always Statement, Procedural Statement | Blocking Statement, Non-Blocking statement | Timing Control Statement: Delay based timing control; Event Based timing control |
| Conditional Statement: If else statement, case statement: casex, casez | Loop: While, do while, for, for each, forever, repeat. | Block statement, Sequential block, Parallel Block |
| De-assign Statement, force statement, Release statement | DESIGN OF DIGITAL CIRCUITS FSM: Mealy machine, Moore machine. | Flip-flops | Counters, Shift Registers. | All combinational and sequential circuits using Verilog |
| VLSI Verification using System Verilog | ||
|---|---|---|
| Design and Verification using System Verilog | ||
| Introduction to System Verilog, Need of system Verilog | Environment of Verification | Data types - 2state, 4 state, enum, string, structure, union, class |
| Array- Fixed array- packed and unpacked array | Dynamic Array, Associative array | Queues |
| Process: - Fork-join, Fork-join any, Fork-join none, Wait-fork | OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation | Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage. |
| Explanation of assertion with example | Explanation of coverage with examples | Working on verification environment |
| Experiential Project Based Learning | ||
| A Prototype Digital System Design using RTL Modeling and SystemVerilog-Based Verification | ||
