Hardware Design Essentials: Verilog to AMBA Protocols
Durations -10 days.
Program Structure
- RTL Designs Using Verilog/VHDL – Prerequisite
- Digital Design Fundamentals – Prerequisite
- Hardware Design Essentials – 6 Days>
- Introduction to Hardware Design Flow
- RTL Design Using Verilog
- Combinational and Sequential Logic Design
- Procedural Blocks & RTL Constructs
- Blocking vs Non-blocking Assignments
- Tasks, Functions, and Parameterized Design
- Synthesizable Coding Guidelines
- On-Chip Interconnects & AMBA Protocols – 4 Days
- Introduction to AMBA Protocols
- AHB (Advanced High-performance Bus)
- APB (Advanced Peripheral Bus)
- AXI-4 (Advanced eXtensible Interface)
Program Outcomes
By the end of this program, learners will be able to:
- Design synthesizable RTL using Verilog
- Understand system-level hardware design concepts
- Explain AMBA architecture and protocol hierarchy
- Differentiate AHB, APB, and AXI-4 protocols
- Interpret address, data, and control signaling in AMBA-based systems
Tools / Platform:
- Xilinx Vivado
Assessment – MCQ’s, Module Test
Project Stream
- RTL Design of Digital Controllers
- AMBA-Based System Integration Concepts
- Protocol-Aware Hardware Design
- Design Readiness for Verification
| RTL Design Using Verilog | ||
|---|---|---|
| Introduction to Verilog HDL | Module Definition and Hierarchical Design | Data Types: wire, reg, integer, parameter |
| Continuous Assignments | Procedural Blocks | Modeling Styles |
| Combinational Logic Modeling Sequential Logic Modeling |
Blocking vs Non-blocking Assignments | Conditional Statements, Looping Constructs |
| Tasks and Functions | Design of a combinational circuit | Design of a sequential circuit |
| Finite State Machine (FSM) Design | Moore and Mealy FSM Implementation | Avoiding Latches and Race Conditions |
| Verification of On-Chip Protocols | ||
| Introduction to AMBA Protocols | AMBA Architecture | Types of AMBA Protocols |
| AHB protocol overview and signal behavior | Address, data, and control phases | APB protocol overview and transfer states |
| Read and write transactions | AXI-4 protocol overview | Read/write and burst transactions |
