Functional Verification of On-Chip Interface using System Verilog
Durations -10 days.
Program Structure
- RTL Designs Using Verilog/VHDL – Prerequisite
- OOPs Concepts of C++ Programming – Prerequisite
- System Verilog Essentials – 6 days
- System Verilog Basics & Data Types
- Procedural Blocks & RTL Constructs
- Interfaces, Randomization & Constraints
- Verification-Oriented Features
- Verification of On-Chip Protocols – 4 Days
- Introduction to AMBA Protocols
- AHB (Advanced High-performance Bus)
- APB (Advanced Peripheral Bus)
- AXI-4 (Advanced eXtensible Interface)
Program Outcomes
By the end of this program, learners will be able to:
- Apply SystemVerilog fundamentals and verification-oriented features to develop structured, reusable, and synthesizable RTL and verification code
- Design and implement SystemVerilog-based testbenches using procedural blocks, interfaces, randomization, constraints, and object-oriented concepts
- Verify on-chip bus protocols (AHB, APB, AXI-4) by validating functional correctness and protocol compliance using SystemVerilog methodologies
Tools / Platform:
- EDA Playground
Assessment – MCQ’s, Module Test
| System Verilog Essentials | ||
|---|---|---|
| Introduction to SystemVerilog vs Verilog | Data types: logic, bit, int, byte, shortint, longint | Packed vs unpacked arrays |
| Enumerations (enum) and structures (struct) | Type casting and typedef | Blocking vs non-blocking assignment |
| Procedural control statements (if, case, loops) | Tasks and functions | SystemVerilog interfaces and benefits |
| Classes, objects, constructors | Object-Oriented Programming basics | Randomization and constraints |
| Mailbox and event mechanisms | Testbench structure and reuse concepts | Testbench demonstration |
| Verification of On-Chip Protocols | ||
| Introduction to AMBA Protocols | AMBA Architecture | Types of AMBA Protocols |
| AHB protocol overview and signal behavior | SystemVerilog testbench architecture for AHB | Verification of address, data, and control phases |
| Functional coverage for AHB transfers and bursts | APB protocol overview and transfer states | SystemVerilog testbench for APB slave verification |
| Verification of read and write transactions | Functional coverage for APB access types | AXI-4 protocol overview and channel architecture |
SystemVerilog testbench for AXI-4 master/slave
Verification of read/write and burst transactions
Functional coverage for AXI-4 channels and responses
