Python Edge –Applied ML Internship
Duration: 4 Weeks
Project Training – Offline / Online
Program HIGHLIGHTS:
- Covers SystemVerilog concepts and verification methodologies.
- Includes testbench architecture, assertions, and coverage.
- Hands-on labs from RTL to complete testbenches.
- Introduces UVM and functional verification strategies.
- Final project on protocol/interface verification using SV.
Outcomes:
- Write synthesizable SystemVerilog for digital design and SystemVerilog testbenches for verification.
- Apply constrained randomization and assertions (SVA).
- Measure and analyze functional coverage.
- Design modular verification environments (with drivers/monitors).
- Execute and debug real-world verification projects.
Project stream:
- Apply machine learning algorithms like SVM, Random Forest, and K-Means to real-world datasets.
- Implement complete ML pipelines: preprocessing, modeling, and evaluation.
- Focus on feature engineering, hyperparameter tuning, and model interpretation.
- Deploy final models using Streamlit and version control with GitHub.
Platform:
- Python 3.x, NumPy, Pandas, Matplotlib, Seaborn, Scikit-learn
- Jupyter Notebook, VS Code, Google Colab
PROJECT DEVELOPMENT – 10 Weeks
Project Phase-1: Research, Planning, and Initial Development
Focus: Learn verification concepts and build core components.
- SystemVerilog basics and testbench structure
- Randomization, assertions, and coverage
- Develop verification plan and DUT (Design Under Test) interface
Outcome: Functional SystemVerilog testbench ready for verification
Project Phase-2: Development, Testing, and Refinement
Focus: Complete functional verification project.
- Develop transaction, driver, monitor, and checker
- Integrate assertions, coverage, and run simulations
- Debug, analyze results, and present final report
Outcome: Verified design with coverage and performance metrics
