Domain-Specific Training in VLSI Design & Verification
Durations – 300 Hrs.-Online & Offline
Program Objective
VLSI Chip and ASIC Design program provides a strong foundation in
analog and digital electronics combined with essential programming
skills in C and C++. Students learn RTL design and simulation using
Verilog for digital systems and gain practical experience with on-chip
protocols and FPGA implementation.
Advanced training in System Verilog equips learners with verification
techniques crucial for modern hardware design. Hands-on projects and
lab sessions reinforce theoretical knowledge with real-world
applications. Students will be prepared for roles in VLSI design,
verification, and embedded systems engineering.
Program Structure
Semester 3: Core Engineering
- Digital Hardware Familiarization
Semester 4: Core Programming Fundamentals
- Mastering OOP using C++ & Competitive problem solving
- Linux System Programming using C
- RTL Coding with Verilog
- On-Chip Protocols Design
- FPGA Programming
- Design and Verification using System Verilog
- Capstone Project: RTL to Deployment
Program Outcome
- Build a strong foundation in digital electronics, structured programming (C/C++), and HDL-based design using Verilog
- Design, simulate, and implement digital systems and on-chip communication protocols on FPGA platforms, applying RTL design principles
- Develop and verify complex digital designs using SystemVerilog, culminating in end-to-end hardware deployment and functional validation
Project stream
VLSI Design
- Design and Simulation of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation and Verification of Digital Controllers, ALU Cores and Protocols such as UART, SPI, I2C, AXI4 on FPGA Board
- SV Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
SW &HW Platform
- Ubuntu (Linux OS, with GCC compiler)
- WSL (Windows Subsystem for Linux)
- Code::Blocks, VSC, Dev-C++
- XILINX VIVADO
- Artix7 FPGA Board, ZYNQ SOC Board
- Questasim / EDA Playground
Semester 3 : Core Engineering
Digital Hardware Familiarization – 40 hrs. – 7 Days – 1Weeks ( Online / Recording )
Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics
Diodes, Rectifiers, Zener & Clamping Circuits
BJTs and MOSFETs (Switching & Amplification)
Operational Amplifiers (Op-Amps), Filters
Digital Electronics & Logic Design: Number Systems & Boolean Algebra
Logic Gates, Multiplexers
Comparators, Encoders/Decoders
Flip-Flops, Counters, Shift Registers,
FSMs, Timing Analysis Basics
Assessment – Module Test – MCQ, Theory
Technical Mock
Semester 4 : Core Programming Fundamentals
Mastering OOP using C++ & Competitive problem solving – 60 hrs. – 10 Days – 2Weeks
Basic input / output: cin, cout, >> and << operators, endl, setw
Understanding namespace Introduction to Object-Oriented Programming
Classes and objects, Encapsulation, Data hiding, abstraction
Semester 5 : VLSI Design
RTL Coding with Verilog – 60 hrs. – 10 Days – 2 Weeks
| Introduction to VLSI: Fundamentals of VLSI | Design Methodology | Verilog data types, Verilog Operators |
| Gate Level Modeling: Gate Instantiate | Design RTL From logic Diagram, Logic Gate primitive | Delay in Gate level Design |
| Data Flow Modeling: Operators in Data Flow | Continuous Assignment (assign statement) | Boolean Equations Representation |
| Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator? | Procedural continuous Assignment Statement |
| Procedural vs Continuous Assignment | Parameterized Data Flow Design Delay Modeling in Data Flow |
Case Studies / Examples (ALU, Adders, MUX, Encoders) |
| Behavioral Modeling: Structured procedural Statement: Always Statement, Procedural Statement | Blocking Statement, Non-Blocking statement | Timing Control Statement: Delay based timing control; Event Based timing control |
| Conditional Statement: If else statement, case statement: casex, casez | Loop: While, do while, for, for each, forever, repeat. | Block statement, Sequential block, Parallel Block |
| De-assign Statement, force statement, Release statement | Design of Digital Circuits FSM: Mealy machine, Moore machine | Flip-flops, Counters, Shift Registers |
| All combinational and sequential circuits using Verilog, CRC checking, PWM | Design of Digital Circuits: FSM: Mealy machine, Moore machine | Useful Of Modeling Technique, All combinational and sequential circuit using Verilog |
| Project - Advanced project & Demo | Assessment – Module Test – MCQ, Theory | Technical Mock |
Semester 6 : On-Chip Protocol and Hardware Design
On-Chip Protocols Design – 20 hrs. – 3 Days – 0.5 week
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol, I2C (Inter Integrated Circuit) protocol | AXI4 (Advanced extensible Interface 4) protocol |
FPGA Programming – 36 hrs. – 6 Days – 1 Weeks
| Introduction to FPGA, FPGA Architecture | CLB, I/O blocks, Interconnects | CPLD, FPGA, FPGA Working, Design Flow, Tool Understanding |
| working Designing basic FPGA example (Adders, Subtractors, Counter) | Implementation of all the combinational circuits on FPGA | Implementation of Flip-flops on FPGA |
| Implementation of Counters - up counter, down counter, up-down counter, mod-counter, Johnson counter, ring counter | Realization of Shift Registers Demonstration of a Project on FPGA |
Realization of FSM: Mealy machine, Moore machine, Designing with VIO and ILA |
| Assessment – Module Test – MCQ, Theory | Technical Mock |
Semester 7: VLSI Verification using System Verilog
Design and Verification using System Verilog – 80 hrs. – 15 Days – 3 weeks
| Introduction of System Verilog, Need of system Verilog | Environment of Verification | Data types - 2-state, 4-state, enum, string, structure, union, class |
| Array - Fixed array - packed and unpacked array | Dynamic Array, Associative array | Queues |
| Process: - Fork-join, Fork-join any, Fork-join none, Wait-fork | OOPS - Inheritance, Polymorphism, Data hiding, Encapsulation | Class - Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage. |
| Explanation of assertion with example | Explanation of coverage with example | Working on verification environment |
| Project - Advanced project & Demo | Assessment – Module Test – MCQ, Theory | Technical Mock |
