Digital Circuit Design &
STA Mastery – 120 Hrs
Duration: 120 Hrs
Level 1 – 60 Hrs
Level 2 – 60 Hrs
Program Outcomes:
- Apply gate, dataflow, and behavioral modeling to develop synthesizable RTL modules.
- Implement FSM-based control logic using Moore or Mealy machine design principles.
- Understand the importance of timing analysis and its impact on functional correctness.
- Perform STA using industrial constraints and analyze slack, skew, and violations.
- Gain hands-on experience in the timing closure process and learn to interpret STA reports for design improvement
Modules:
Level 1 – Digital Circuit Design using Verilog – 60 Hrs:
Module: RTL Coding with Verilog HDL
- VLSI fundamentals, design methodology
- Different styles of modeling
- Conditional and procedural statements, delay modeling
- Advanced RTL designs
Level 2 – Static Timing Analysis – 60 Hrs:
Module: Timing Closure and STA for VLSI Design System Verilog
- RTL Preparation and Clocking
- Synthesis and Optimization
- Fundamentals of Static Timing Analysis
- STA Tools and Reports
Experiential Project Based Learning
- A Prototype Digital System Design with RTL Modeling and Timing Analysis using STA Flow
Tools / Platform:
- Xilinx Vivado
- OpenTimer
- Yosys
| Level 1: Digital Circuit Design using Verilog (60 Hours) | ||
|---|---|---|
| Module: RTL Coding with Verilog HDL | ||
|
Introduction to VLSI Fundamentals of VLSI Design Methodology Verilog Data Types & Operators |
Gate Level Modeling Gate Instantiation Logic Gate Primitive Delay in Gate Level Design RTL from Logic Diagram |
Data Flow Modeling Operators, Continuous Assignment Boolean Equation Representation Ternary Operator, Procedural Assignment Delay Modeling, Parameterized Design |
| Examples: ALU, Adders |
Examples: MUX, Encoders |
Use Case: Case Studies & RTL Practice |
|
Behavioral Modeling Always Statement, Procedural Statements Blocking/Non-Blocking Statements Timing Control (Delay/Event Based) |
Control Structures if-else, casex, casez Loops: while, for, repeat, forever |
Blocks & Signals Sequential & Parallel Blocks De-assign, Force, Release Statements |
|
Design of Digital Circuits FSM: Mealy & Moore Machines Flip-Flops |
Counters, Shift Registers Combinational & Sequential Designs |
CRC Checking PWM Implementation |
| Level 2: Static Timing Analysis (60 Hours) | ||
|---|---|---|
| Module: Timing Closure and STA for VLSI | ||
|
RTL Linting and CDC RTL Synthesis Flow |
Clocking Concepts Clock Domain Synchronization |
Timing Constraints Overview Writing Constraints |
|
Submicron Process Nodes Technology Libraries |
Design Optimization Netlist Generation |
Logic Equivalence (LEC) Formality Verification |
|
STA Overview Terminologies, Clock, Reset, Delay |
Timing Checks: Setup, Hold, Metastability |
Analysis of Combinational & Sequential Logic |
|
Understanding Timing Paths Path Types |
STA Flow Understanding |
STA Inputs/Outputs Design Rule Violations |
| Timing Exceptions | PVT Corners | OCV (On-Chip Variation) |
| Experiential Project-Based Learning | ||
| Prototype Digital System Design with RTL Modeling and Timing Analysis using STA Flow | ||
