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PG Diploma in VLSI Design & ASIC Verification

100% JOB Assured with Globally Accepted Certificate

Duration: 500+60 Hrs.

Eligibility: BE, B.Tech, ME, M.Tech

Intermediate

Program Overview
Core Engineering
  • Digital Hardware Familiarization
    • Digital Electronics, Logical circuit design
    • Timing analysis
Core Programming
  • RTL Coding with Verilog
  • On-Chip Protocols Design
  • FPGA Programming
VLSI Design
  • RTL Coding with Verilog
  • On-Chip Protocols Design
  • FPGA Programming

SPECIALIZATIONS:

  • Design & Verification using SystemVerilog
  • ASIC Verification using UVM
  • On-Chip Protocols Verification
  • Python Scripting
  • TCL Scripting
  • Static Timing Analysis
Projects Stream:
  • QuestaSim / EDA Playground
  • Yosys, OpenTimer
  • Artix-7 FPGA Board
  • Zynq SoC Board

Capstone Projects

  • UART, SPI, I2C, AXI4 Protocol Design
  • FPGA Design & Verification
  • RTL to Silicon Projects
  • SystemVerilog Verification
  • UVM-Based Verification
  • End-to-End Functional Verification

Industry Job Roles

  • Industry-Recognized Certifications
  • RTL Design & FPGA Implementation
  • SystemVerilog & UVM Verification
  • Python & TCL Scripting
  • STA & Synthesis Flow
  • Placement & Interview Preparation
Enquire Now Download Brochure Training Calendar Recent Placements
Core Engineering
Module 1 • Digital Hardware Familiarization 40 hrs

Key Skills: Analog circuits · Digital logic · FSMs · Timing analysis · Number systems · Boolean algebra

Analog electronics: Ohm's Law, RC circuits, power supply basics Diodes, rectifiers, Zener & clamping circuits BJTs and MOSFETs: switching, amplification, CMOS
Operational amplifiers (Op-Amps), filters and comparators Digital electronics & logic design: number systems & Boolean algebra Logic gates, multiplexers, encoders and decoders
Flip-flops, counters and shift registers Finite state machines Basics of timing analysis
Learner Outcome: Understand analog and digital electronics fundamentals, logic design concepts, and timing analysis essential for VLSI design.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
Module 2 • Mastering C Programming Self-Study

Key Skills: Program structure · Arrays · Strings · Searching & Sorting · Pointers

Simple C program structure Literals, constants, variables and data types Arrays: 1D and 2D
Sorting and searching algorithms Strings and string functions
Learner Outcome: Build foundational C programming skills to support embedded and hardware abstraction layer development.
Module 3 • Mastering OOP using C++ 60 hrs

Key Skills: Classes · Inheritance · Polymorphism · Templates · STL · Smart Pointers · Lambda

Introduction to Object-Oriented Programming Understanding OOP concepts Basic input/output: cin, cout, endl
Understanding namespace Classes and objects Abstraction
Encapsulation Access specifiers – private and protected This pointer
Constructors and destructors Friends and operator overloading Inheritance
Run-time polymorphism Exception handling Lambda expressions
Smart pointers Templates STL problem solving using HackerRank
Learner Outcome: Design modular and reusable applications using object-oriented principles, STL, and modern C++ features.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
▶ Capstone Project • Capstone Project – Programming • Multi-Client Chat Application, Memory Leak Detection Toolkit, E-Commerce Cart Simulator
★
CERTIFICATION MILESTONE · Certification in Programming
VLSI Design
Module 4 • RTL Coding with Verilog 60 hrs

Key Skills: Gate-level · Data flow · Behavioral modeling · FSMs · Timing · Functions & Tasks

Introduction to VLSI: fundamentals and design methodology Verilog data types and operators Gate-level modeling: gate instantiation and logic gate primitives
Design RTL from logic diagram Delay in gate-level design Data flow modeling: operators and continuous assignment
Boolean equation representation Gate-level abstraction using data flow Conditional assignment (ternary operator ? 🙂
Procedural continuous assignment statement Procedural vs continuous assignment Parameterized data flow design and delay modeling
Case studies: ALU, adders, MUX, encoders Behavioral modeling: always statement and procedural statements Blocking and non-blocking statements
Timing control: delay-based and event-based Conditional statements: if-else, case, casex, casez Loop constructs: while, do-while, for, foreach, forever, repeat
Block statements: sequential block and parallel block De-assign, force and release statements All combinational and sequential circuits using Verilog
Flip-flops, counters and shift registers Functions, tasks and generate statements FSM: Mealy machine and Moore machine
CRC checking and PWM
Learner Outcome: Design and simulate digital circuits using all Verilog modeling styles — gate-level, data flow, and behavioral — including FSMs and complex sequential logic.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
Module 5 • On-Chip Protocols Design 20 hrs

Key Skills: UART · I2C · SPI · AMBA architecture · AXI4

Introduction to serial communication protocols UART (Universal Asynchronous Receiver Transmitter) protocol I2C (Inter-Integrated Circuit) protocol
SPI (Serial Peripheral Interface) protocol AMBA architecture introduction AXI4 (Advanced eXtensible Interface 4) protocol
Learner Outcome: Design and implement on-chip communication protocols including UART, I2C, SPI, and AXI4 using RTL modeling.
Module 6 • FPGA Programming 40 hrs

Key Skills: FPGA architecture · CLB · Combinational & sequential circuits · FSM on FPGA · VIO · ILA

Introduction to FPGA and FPGA architecture CLB, I/O blocks and interconnects CPLD vs FPGA: working, design flow, tool understanding
Designing basic FPGA examples: adders, subtractors, counters Implementation of all combinational circuits on FPGA Implementation of flip-flops on FPGA
Implementation of counters: up, down, up-down, mod, Johnson, ring Realization of shift registers on FPGA Realization of FSM: Mealy machine and Moore machine
Designing with VIO and ILA Demonstration of a complete project on FPGA
Learner Outcome: Implement and verify digital designs on FPGA hardware, including combinational, sequential, and FSM-based circuits using Xilinx Vivado.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
▶ Capstone Project • Capstone Project – Digital Design Innovators: RTL to Realization • Design, simulation, and FPGA implementation of UART, SPI, I2C, AXI4 controllers
★
CERTIFICATION MILESTONE · Diploma in VLSI Design & Verification
Specializations
Module 7 • Design & Verification using System Verilog 100 hrs

Key Skills: SV data types · OOP · Randomization · Functional coverage · Assertions · Testbench

Introduction to System Verilog and need for System Verilog Environment of verification Data types: 2-state, 4-state, enum, string, structure, union, class
Arrays: fixed array (packed and unpacked) Dynamic array Associative array
Queues Process: fork-join, fork-join any, fork-join none, wait-fork OOP: inheritance, polymorphism, data hiding, encapsulation
Class: deep copy, shallow copy, overriding class Functional coverage and cross coverage Explanation of assertions with examples
Explanation of coverage with examples Working on a complete verification environment
Learner Outcome: Develop functional verification environments using SystemVerilog OOP, constrained randomization, assertions, and coverage-driven verification.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
Module 8 • ASIC Verification using UVM 40 hrs

Key Skills: UVM base classes · UVM phases · TLM ports · Testbench components · Config DB

Introduction to UVM: why UVM UVM objects: base classes UVM macros and base class methods
UVM phases UVM Config DB UVM reporting mechanism
UVM TLM ports and analysis UVM FIFO and socket concept UVM callbacks
UVM testbench components UVM testbenches
Learner Outcome: Build industry-standard UVM testbenches and verify complex digital designs using UVM methodology.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
Module 9 • On-Chip Protocols Verification 40 hrs

Key Skills: UART verification · SPI verification · I2C verification · AXI4 verification

UART (Universal Asynchronous Receiver Transmitter) protocol verification SPI (Serial Peripheral Interface) protocol verification I2C (Inter-Integrated Circuit) protocol verification
AXI4 (Advanced eXtensible Interface 4) protocol verification
Learner Outcome: Verify on-chip communication protocols using SystemVerilog and UVM-based functional verification environments.
▶ Capstone Project • Capstone Project – Functional Verification: System Verilog to UVM • SV and UVM verification of UART, SPI, I2C, AXI4 protocols
Module 10 • Python Scripting for EDA 40 hrs

Key Skills: Python fundamentals · EDA automation · Report parsing · Testbench scripting · Visualization

Python fundamentals Data structures and file handling Regular expressions & pattern matching
Scripting for EDA automation Parsing reports and timing files Visualization & reporting
Python for verification & testbenches
Learner Outcome: Use Python scripting to automate EDA workflows, parse simulation and timing reports, and enhance verification productivity.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
Module 11 • Linux & Scripting 20 hrs

Key Skills: Linux Commands · Shell Scripting · Automation · Environment Setup

Introduction to Linux Linux commands Shell scripting
Learner Outcome: Master Linux environments and automate tasks using shell scripting to streamline engineering and verification workflows.
✎ Assessment: Final Project Test (Assignment, MCQ, Theory & Lab) · Technical Mock
▶ Capstone Project • Capstone Project – Advanced VLSI Verification • 40 hrs · End-to-end UVM verification of complex IP/SoC protocols
Module 12 • Static Timing Analysis (STA) 40 hrs

Key Skills: RTL linting · CDC · Synthesis · Timing paths · Setup & hold · PVT corners · LEC

Introduction to RTL linting and CDC Introduction to RTL synthesis flow Clocking and clock domain synchronization concepts
Timing constraints overview Writing constraints Submicron process nodes and technology library understanding
Synthesis process Design optimization and netlist generation Logic equivalence check (LEC) / formality verification
Introduction to Static Timing Analysis and terminologies Timing fundamentals: clock, reset, delays Timing checks: setup, hold, metastability
Understanding timing paths and types of timing paths Timing analysis for combinational & sequential logic circuits STA flow: inputs and outputs
Design rule violations Timing exceptions PVT corners and OCV
Understanding setup and usage of EDA tools for synthesis and STA
Learner Outcome: Perform static timing analysis, interpret timing reports, handle timing exceptions, and use EDA tools for synthesis and signoff verification.
✎ Assessment: Module Test (MCQ & Theory) · Technical Mock
★
CERTIFICATION MILESTONE · PG Diploma in VLSI Design & ASIC Verification

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FAQs

The course is designed for:

  • Engineering graduates in Electronics, Electrical, and Circuit branch students.
  • Individuals with a foundational understanding of digital electronics and programming.

Yes, a basic understanding of programming concepts is beneficial. Familiarity with hardware description languages like Verilog or SystemVerilog is advantageous but not mandatory.

The program includes comprehensive modules on:

  • Digital Design: Verilog, SystemVerilog
  • Verification Techniques: UVM, SV
  • Protocol Verification: UART, I2C, SPI, AXI4
  • FPGA Implementation: Hands-on with Artix boards
  • Design Methodologies: RTL design, synthesis, and timing analysis

Students gain practical experience with industry-standard Electronic Design Automation (EDA) tools, including:

  • Cadence: For schematic capture and layout
  • Synopsys: For synthesis and simulation
  • Mentor Graphics: For PCB design and verification
  • ModelSim: For simulation of HDL designs

Yes, Cranes Varsity offers live instructor-led online sessions, allowing flexibility for remote learning.

Upon successful completion, students receive a Postgraduate Diploma Certificate from Cranes Varsity, recognized within the industry.

 

Yes, Cranes Varsity provides 100% job assistance, leveraging partnerships with over 500 hiring companies. Placement support includes:

  • Resume preparation
  • Mock interviews
  • Access to job opportunities in VLSI design, verification, and related fields

Ideal candidates should have:

  • A Bachelor’s degree in Electronics, Electrical Engineering, Computer Science, or related fields
  • A basic understanding of digital and analog electronics
  • Familiarity with HDLs is advantageous but not mandatory for beginners

Graduates can explore various roles, such as:

  • VLSI Design Engineer
  • Verification Engineer
  • RTL Design Engineer
  • ASIC Designer
  • FPGA Designer
  • Embedded Systems Engineer with a focus on hardware

To enroll:

  • Online: Fill out the application form on the official website, and a dedicated admission counselor will contact you.
  • Offline: Visit the Cranes Varsity campus for direct inquiries and enrollment assistance.

The exact fee details are not publicly listed. For information on course fees and available scholarships, please contact Cranes Varsity directly.

Cranes Varsity offers a Scholarship Test. For eligibility criteria, test dates, and details on fee waivers, please reach out to their admissions team.

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