Wise Training in VLSI Chip & ASIC Design
Program Structure
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Semester 3 – Core Engineering
- Digital Hardware Familiarization
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Semester 4 – Core Programming Fundamentals
- Mastering OOP using C++ & Competitive Problem Solving
- Linux System Programming using C
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Semester 5 – VLSI Design
- RTL Coding with Verilog
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Semester 6 – On-Chip Protocol and Hardware Design
- On-Chip Protocol Design
- FPGA Programming
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Semester 7 – VLSI Verification using System Verilog
- Design and Verification using System Verilog
- Verification using UVM
- Capstone Project: RTL to Deployment
Pre-requisites
- Eligibility: 3rd, 4th, 5th, 6th, 7th Semester B.E / B.Tech students
- Basic understanding of digital electronics and logic design
- Familiarity with any programming language (C/C++ preferred)
- Logical thinking and problem-solving skills
- No prior VLSI experience required
Program Outcomes
- Build a strong foundation in digital electronics, structured programming (C/C++), and HDL-based design using Verilog
- Design, simulate, and implement digital systems and on-chip communication protocols on FPGA platforms, applying RTL design principles
- Develop and verify complex digital designs using System Verilog, culminating in end-to-end hardware deployment and functional validation
Project Stream
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VLSI Design
- Design and simulation of digital controllers, CPU cores, and protocols: UART, SPI, I2C, AXI4
- Design, simulation, implementation, and verification of ALU cores and protocols on an FPGA board
- SystemVerilog verification of digital controllers, CPU cores, and protocols: UART, SPI, I2C, AXI4
SW & HW Platforms
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Software & OS
- Ubuntu (Linux OS, GCC Compiler) · WSL (Windows Subsystem for Linux)
- Code::Blocks, VS Code, Dev-C++
- Xilinx Vivado · Artix-7 FPGA Board · Zynq SoC Board
- Questasim / EDA Playground
