Digital Circuit Design for VLSI Systems with On-Chip Communication
Duration – 10 Days.
Program Structure
- Digital Electronics– Prerequisite
- Basics of C Programming – Prerequisite
- RTL Coding with Verilog – 4 Days
- Data Types & Operators
- Module structure
- Three Modeling Styles
- Combinational Circuits
- Sequential Circuits
- RTL Design of Serial Communication Protocols – 3 Days
- UART (Universal Asynchronous Receiver Transmitter)
- I2C (Inter Integrated Circuit)
- SPI (Serial Peripheral Interface)
- RTL Design of On-Chip Protocols – 3 Days
- AHB (Advanced High-performance Bus)
- APB (Advanced Peripheral Bus)
- AXI-4 (Advanced eXtensible Interface)
Project Stream
Design and Simulation of Digital Controllers, CPU Cores
Program Outcomes
By the end of this program, learners will be able to:
- Understand RTL design fundamentals using Verilog, including data types, operators, modeling styles, and module structures
- Design and implement combinational and sequential digital circuits using synthesizable RTL coding practices
- Develop RTL implementations of serial communication protocols (UART, I2C, SPI) and on-chip bus protocols (AHB, APB, AXI4)
- Apply industry-relevant RTL design methodologies to build modular, reusable, and protocol-compliant hardware designs for VLSI and SoC applications
Tools / Platform:
XILINX VIVADO
Assessment – MCQ, Module Test
| RTL Coding with Verilog | ||
|---|---|---|
| HDL vs Programming Languages | RTL Design Concept and Design Flow | Simulation vs Synthesis |
| Verilog Design Abstraction Levels | Verilog Data Types & Operators | Module Declaration and Port Lists |
| Input, Output, Inout Ports | Continuous Assignments (assign) | Procedural Blocks (always, initial) |
| Blocking vs Non-blocking Assignments | Sensitivity Lists and always @(*) | Generate and Parameterized Modules |
| Structural Modeling | Dataflow Modeling | Behavioral Modeling |
| Comparison and Use-Cases of Each Style | Combinational Logic Concepts | Multiplexers and Demultiplexers |
| Encoders and Decoders, Comparators | Adders and Subtractors | Arithmetic Logic Unit (ALU) Basics, Latch Inference and How to Avoid It |
| Sequential Logic Fundamentals | Finite State Machines (FSMs) | Moore vs Mealy Machines |
| RTL Design of Serial Communication Protocols | ||
|---|---|---|
| UART architecture and frame format | Baud rate generation and timing control | UART transmitter and receiver RTL design |
| FSM implementation | I2C bus architecture and signal operation | Start/stop conditions and addressing modes |
| Read/write transactions with ACK/NACK | I2C controller FSM and clock stretching | SPI architecture and signal interface |
| SPI modes (CPOL/CPHA) and timing | SPI master and slave RTL design | Full-duplex data transfer and chip-select control |
| RTL Design of On-Chip Protocols | ||
| AHB architecture and signal overview | AHB master–slave communication | Address, data, and control phase operation |
| RTL design of read/write and burst transfers | APB architecture and interface signals | APB state machine and transfer phases |
| Read and write transaction timing | RTL design of APB slave interface | AXI-4 architecture and channel overview |
| AXI-4 handshaking and transaction types | Burst transfers and address alignment | RTL design of AXI-4 read/write channels |
