RTL Design with Verilog
Project
Internship Program
Duration – 15 Weeks
Project Training – Offline / Online – 5 WEEKS
Project Development – Offline/ Online – 10 WEEKS
PROGRAM HIGHLIGHTS:
- Introduction to VLSI design flow and Verilog HDL fundamentals.
- Hands-on learning of gate-level, dataflow, and behavioral modeling.
- Design of combinational and sequential digital circuits using Verilog.
- Implementation of UART, SPI, I²C.
- System-level integration of multiple RTL modules.
- Project development and student presentations
OUTCOMES:
- Model digital systems using Verilog across various abstraction levels
- Simulate and debug designs using professional EDA tools
- Design synthesizable communication protocol modules
- Integrate functional blocks into complete digital systems
- Demonstrate and present working RTL-based projects.
PROJECT EXAMPLES:
- ALU & Code Converters (Digital system design)
- FSM-Based Controllers (Traffic light, vending machine, password lock)
- Sequential Logic Projects (Counters, shift registers, clock dividers)
- Protocol Implementations (UART, SPI, I2C, AXI4)
- System Integration Projects (Memory interface, CRC checker, mini SoC
TOOLS AND RESOURCES:
- XILINX VIVADO
- Questasim / EDA Playground
PROJECT DEVELOPMENT – 10 Weeks
Project Phase-1: Planning & Environment Development
- Focus: Learn verification concepts and build testbench components.
- SystemVerilog basics and OOP
- Testbench architecture, randomization, assertions, and coverage
- Develop plan and connect basic DUT
- Outcome: Functional SystemVerilog testbench setup
Project Phase-2: Implementation, Testing & Report
- Focus: Full verification project for a given design.
- Develop transaction, driver, monitor
- Add assertions and coverage
- Debug, simulate, and present final results
- Outcome: Verified design with coverage report and final demo
