VLSI Chip & ASIC Design
Semester-wise Duration – 60 Hrs/75 Hrs per ( 300 Hrs )
Program Objective:
VLSI Chip and ASIC Design program provides a strong foundation in
analog and digital electronics combined with essential programming
skills in C and C++. Students learn RTL design and simulation using
Verilog for digital systems and gain practical experience with on-chip
protocols and FPGA implementation.
Advanced training in System Verilog equips learners with verification
techniques crucial for modern hardware design. Hands-on projects and
lab sessions reinforce theoretical knowledge with real-world
applications. Students will be prepared for roles in VLSI design,
verification, and embedded systems engineering.
Program Structure
Semester 3: Engineering Primer (60 Hours)
- Analog Electronics
- Digital Electronics
- C Programming
- Object-Oriented Programming Concepts with C++
- Verilog HDL Basics
- RTL Designs of Combinational & Sequential Circuits
- On-Chip Communication Protocols
- FPGA-Based System Design
- System Verilog for Functional Verification
- Verification Environment Development
- Capstone Project: RTL to Deployment
Program Outcomes
- Build a strong foundation in digital electronics, structured programming (C/C++), and HDL-based design using Verilog.
- Design, simulate, and implement digital systems and on-chip communication protocols on FPGA platforms, applying RTL design principles.
- Develop and verify complex digital designs using SystemVerilog, culminating in end-to-end hardware deployment and functional validation.
Experiential Project Based Learning:
Embedded Linux with Pi & Sensors
Project streams
Core Programming
- E-Commerce Application
- Banking Application
- Health Care Sector
- Insurance Policy
SW &HW Platform
- Ubuntu (Linux OS, with gcc compiler)
- WSL(Windows Subsystem for Linux)
- Code::Blocks , VSC , Dev-C++
- XILINX VIVADO,
- Artix7 FPGA Board , ZYNX SOC Board
- Questasim/EDA Playground
| Semester 3: Engineering Primer (60 hours: 30 sessions) | ||
|---|---|---|
| Analog Electronics – (30 Hrs : 15 sessions) | ||
| Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics | Diodes, Rectifiers, Zener & Clamping Circuits | BJTs and MOSFETs (Switching & Amplification) |
| Operational Amplifiers (Op-Amps) | Filters | Comparators |
| Digital Electronics – (30 Hrs : 15 sessions) | ||
| Digital Electronics & Logic Design: Number Systems & Boolean Algebra | Logic Gates, Multiplexers, Encoders/Decoders | Latches and Flip-Flops |
| Counters, Shift Registers | Finite State Machines: Mealey & Moore | Basics of Timing Analysis |
| Semester 4: Core Programming Fundamentals (60 hours: 30 sessions) | ||
| C Programming (30 Hrs : 15 sessions) | ||
| Introduction to CPP: Simple CPP program structure | Literals, Constants, Variables and Data types | Operators with precedence and associativity |
| Control flow statements with Examples | Modular Programming using functions | Arrays |
| Sorting and searching | Strings | |
| Object-Oriented Programming Concepts with C++ (30 Hrs : 15 sessions) | ||
| Introduction to Object-Oriented Programming | Understanding OOP concepts | Basic input/output: cin, cout, endl, >>, and << |
| Understanding namespace | Classes | Objects |
| Abstraction | Encapsulation | Access Specifiers – Private and Protected |
| This pointer | Constructors and Destructors | Friends and operator overloading |
| Inheritance | Run time polymorphism | Exception Handling |
| Lambda Expression | Smart Pointers | Templates |
| STL | Problem Solving using HackerRank | |
| Semester 5: VLSI Design Foundations (60 hours : 30 sessions) | ||
| Verilog HDL Basics - (20 Hrs : 10 sessions) | ||
| INTRODUCTION TO VLSI: Fundamentals of VLSI | Design Methodologies: Top-Down, Bottom-up | Verilog data types |
| Verilog Operators | Typical Module description | Developing a typical test bench |
| RTL Designs of Combinational and Sequential Circuits (40 Hrs : 20 Sessions) | ||
| GATE LEVEL MODELING: Gate Instantiate Design, RTL from Logic Diagram | Delay in Gate level Design | DATA FLOW MODELING: Operators in Data Flow |
| Continuous Assignment (assign statement) | Boolean Equations Representation | Gate-level Abstraction using Data Flow |
| Conditional Assignment (Ternary Operator ? 🙂 | Procedural Continuous Assignment Statement | Procedural vs Continuous Assignment |
| Parameterized Data Flow Design | Delay Modeling in Data Flow | Case Studies / Examples (ALU, Adders, MUX, Encoders) |
| BEHAVIORAL MODELING: Always Statement, Procedural Statement | Blocking vs Non-Blocking Statements | Timing Control Statements: Delay & Event Based |
| Conditional Statements: if-else, case, casex, casez | Loops: while, do while, for, repeat | Sequential & Parallel Blocks |
| De-assign, Force, Release Statements | All combinational circuits: Adders, Multiplexers, Decoders | Flip-flops |
| Counters, Shift Registers | Finite State Machines: Mealy & Moore | CRC checking, PWM |
| Semester 6: On-Chip Protocol and Hardware Design (60 hours: 30 sessions) | ||
| On-chip Communication Protocols – (20 Hrs : 10 sessions) | ||
| UART Protocol | SPI Protocol | I2C Protocol |
| AXI4 (Advanced eXtensible Interface 4) protocol | ||
| FPGA Based System Design – (40 Hrs : 20 sessions) | ||
| Introduction to FPGA | FPGA Architecture | CLB, I/O blocks, Interconnects |
| CPLD, FPGA Design Flow, Toolchain | Designing basic FPGA examples (Adders, Subtractors, Counter) | Implementation of combinational circuits |
| Implementation of Flip-flops | Implementation of Counters (up, down, mod, Johnson, ring) | Realization of Shift Registers |
| Realization of FSM: Mealy, Moore, VIO, ILA | Demonstration of FPGA Project | |
| Semester 7: System Verilog & Project Based Learning (60 hours: 30 sessions) | ||
| System Verilog for Functional Verification – (50 Hrs : 25 sessions) | ||
| Introduction to System Verilog | Verification Environment | Data types: 2state, 4state, enum, string, struct, class |
| Fixed & Dynamic Arrays | Associative Arrays, Queues | OOP: Inheritance, Polymorphism, Encapsulation |
| Processes: fork-join variants | Functional Coverage | Assertions & Examples |
| Verification Environment Development – (10 Hrs : 05 sessions) | ||
| Verification Environment | Testbench Architecture | Driver Creation |
| Generator | Monitor | Scoreboard |
| Experiential Project-Based Learning: RTL to Deployment | ||
| Prototype Digital System Design using RTL Modeling, FPGA Deployment & SystemVerilog Verification | ||
Semester-wise Learning Objectives and Learning Outcomes
Semester 3: Engineering Primer (60 Hours)
- Analog Electronics
- Digital electronics
Learning Objectives with Bloom's Taxonomy
| Si. No. | Learning Objective | Bloom’s Level |
|---|---|---|
| 1 | Identify components and explain their roles in analog and digital circuits | Remember |
| 2 | Analyze circuit behavior involving op-amps, filters, and transistors | Analyze |
| 3 | Apply logic design techniques to build combinational and sequential circuits | Apply |
| 4 | Evaluate circuit performance based on timing and functional analysis | Evaluate |
| 5 | Design and simulate FSM-based systems integrating analog and digital blocks | Create |
Learning Outcomes with Bloom's Taxonomy and Assessment Criteria
| Si. No. | Learning Outcome | Bloom’s Level | Assessment Criteria |
|---|---|---|---|
| 1 | Demonstrate understanding of analog and digital components | Understand | Written quiz or oral explanation identifying components and describing functions |
| 2 | Construct and simulate logic circuits using basic gates | Apply | Practical lab task using circuit simulation software or breadboarding |
| 3 | Analyze timing diagrams and sequential logic behavior | Analyze | Evaluation of timing diagrams in assignments or lab reports |
| 4 | Evaluate the performance of analog circuits under varying conditions | Evaluate | Lab performance assessment or viva on analog behavior |
| 5 | Design and document FSM-based systems using logic blocks | Create | Project submission including schematic, simulation, and design explanation |
Semester 4: Core Programming Fundamentals (60 Hours)
- C Programming
- Object-Oriented Programming Concepts with C++
Learning Objectives with Bloom's Taxonomy
| Si. No. | Learning Objective | Bloom’s Level |
|---|---|---|
| 1 | Implement modular programs using functions, arrays, and structures | Apply |
| 2 | Analyze code for efficiency and potential improvements | Analyze |
| 3 | Apply OOP principles to develop structured and reusable software modules | Apply |
| 4 | Evaluate different sorting and searching algorithms for performance | Evaluate |
| 5 | Design and implement object-oriented applications using advanced C++ features | Create |
