Design Verification using System Verilog
- nasscom and Ministry of Electronics and Information Technology initiative
- Official partner with Cranes Varsity
- Certification from IT-ITeS SSC Council
- Government of India Incentive
Duration– 100 Hours
Certificates
Program Objectives
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- Understand System Verilog for Verification
- Develop Testbenches for RTL Verification
- Apply Advanced Verification Techniques
- Gain practical experience by verifying real-world digital designs
using System VerilogÂ
Program Objectives
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- Ability to design and implement SystemVerilog-based verification environments. ď‚·Â
- Demonstrate skills in debugging verification failures and analyzing functional coverage reports. ď‚·Â
- Apply verification methodologies to validate complex digital circuits. ď‚·Â
- Successfully complete an end-to-end verification project, showcasing real-world verification expertise
Pre-requisites
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- Knowledge of Digital Electronics & Logic Design
- Familiarity withHDL languages (Verilog/VHDL)
- Knowledge of OOPs Concepts
Platforms RequiredÂ
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- Xilinx Vivado Â
- EDA Playground
Topics:
- Introduction to System Verilog
- Evolution from Verilog to System
Verilog - Need for System Verilog in
Verification - Verification Methodologies
- Directed vs. Constraint-Random
Verification - Functional Verification Concepts
- Testbench Architecture Overview
- Components of a Testbench
- Simulation vs. Emulation
- Queues
Hands-on:
- Writing test cases using different data typesď‚·Â
- Implementing and manipulating arrays
- Setting up a System Verilog environment
- Writing and running a simple testbench
Topics:
System Verilog Data Types
- 2-State & 4-State Data Types
- Enumerated Data Types
- String, Structure, and Union
Arrays in System Verilog
- Fixed Arrays (Packed & Unpacked)
- Dynamic Arrays
- Associative Arrays
Hands-on:
- Creating and using classes in SystemVerilog ď‚·
- Implementing inheritance and method overriding
Topics:
System Verilog Process Control
- Fork-Join
- Fork-Join Any
- Fork-Join None
- Wait-Fork
Construct Flow Constructs
- If-Else, Case (casex, casez)
- Loops (For, While, Do-While, Repeat,
Forever)
Hands-on:
- Implementing fork-join in concurrent processes
- Writing different loop constructs for verification
Topics:
Introduction to OOP in Systems Verilog
Class & Object Concepts
OOP Features
- Inheritance
- Polymorphism
- Encapsulation & Data Hiding
Class Methods & Overriding:
- Deep Copy vs. Shallow Copy
Hands-On:
- Creating and using classes in SystemVerilog ď‚·
- Implementing inheritance and method overriding
Topics:
System Verilog Assertions
- Immediate & Concurrent Assertions
- Property & Sequence Blocks
- Examples of Assertions in Design Verification
Functional Coverage Concepts
- Covergroups & Coverpoints
- Cross Coverage
- Coverage Bins & Thresholds
Hands-On:
- Writing simple assertions to check design properties
- Implementing functional coverage models
Topics:
SystemVerilog Verification Components
- Generator, Driver, Monitor, Scoreboard
Testbench Development
- Stimulus Generation & Transaction-Level
Modeling (TLM) - Handling Transactions & Checkers
Hands-On:
- Developing a complete testbench architecture ď‚·
- Writing test sequences for a given design
Project Scope:Â
- Selecting a real-world verification challenge
(e.g., UART, SPI, or simple RISC processor)
Developing a complete verification
environment
- Writing System Verilog assertions
- Implementing functional coverage
- Creating and testing a modular
testbench
Final Demonstration & Review
Hands-on:
- Â Implementing a verification project using System Verilog
- Debugging and optimizing the testbench
