RTL Design using Verilog HDL
- nasscom and Ministry of Electronics and Information Technology initiative
- Official partner with Cranes Varsity
- Certification from IT-ITeS SSC Council
- Government of India Incentive
Duration– 50 Hour
Certificates
Objectives
- Have strong fundamentals in HDL Coding.
- Gain exposure to industry standards of Verilog HDL flow
- Understanding Different Coding Methodologies
- To gain an Understanding of RTL coding for synthesis
- Write Verilog test fixtures for simulation
Tools and Resources used
- Xilinx VivadoTool
Digital Electronics Basics
- CombinationalCircuits.
- SequentialCircuits
- Designofbasicgatesusingmux
Digital Electronics Basics
- Counterdesign
- Designofdigitalcircuitsforgivenconcepts
Introduction to VLSI
- DesignFlowofIC
- HDL
- BasicconceptofVerilogHDL.
- DesignBlock
- Stimulusblock
Levels of Modeling
- SwitchLevel
- GateLevel
Levels of Modeling
- Dataflow
- Behavioral
Introduction to Procedural concepts
- Conditional statements.
- Loop Constructs.
Implementation of Circuitusing Verilog
- CombinationalCircuits (SwitchLevel,GateLevel,Dataflow,Behaviorallevelmodeling)
Implementation of Circuitusing Verilog
- SequentialCircuits(GateLevel,Dataflow,Behaviorallevelmodeling)
Design of Test Bench
- IntroductionToTest Bench
- Implementation of test benches for combinational circuits
- Implementation of test benches forsequential circuits
Implementation of Asynchronous Counterusing Verilog
- Up Counter
- Down counter
- Updowncounte
Implementation of Synchronous Counterusing Verilog
- Up Counter
- Down counter
- Updown counter
Implementation of Counterusing Verilog
- Johnson counter
- Ring counter
- Excess3 counter
Implementation of Shift register using Verilog
- SISO
- SIPO
- PISO
- PIPO
Implementation of Shift register using Verilo
- Arithmetic Shift operator usage for shift operation in Verilog HDL
Implementation of Circuit using Verilog
- ALU
- MACunit
Design of FSM using Verilog
- Mealy Machine
- FSM based Sequence detector(Mealy)
Design of FSM using Verilog
- Moore Machine.
- FSM based Sequence detector(Moore)
Memory Modeling
- Design of Memory using RTL coding
- RAM Design (single and dualport)
- ROM Design
Timer
- Introduction toTimer
- implementation of timer using Verilog HDL
PWM
- Introduction to PWM
- Implementation of PWM using Verilog HDL
Frequency divider
- Introduction frequency divider
- Implementation of frequency divider using Verilog HDL
Design of FIFO
- Introduction to FIFO
- Implementation of FIFO using Verilog HDL
Design of Protocols
- Introduction to UART
- Baudrate calculation
- Advantages and disadvantages of UART
- Design of UART using Verilog HDL
SPI
- Introduction to SPI
- Advantage sand disadvantages of UART
- Design of SPI using Verilog HDL
