RTL Design Using Verilog
- nasscom and Ministry of Electronics and Information Technology initiative
- Official partner with Cranes Varsity
- Certification from IT-ITeS SSC Council
- Government of India Incentive
Duration– 100 Hours
Certificates
Program Objectives
- Understand RTL Design Principles
- Develop expertise in Gate-Level, Dataflow, and Behavioral
Modeling techniques. - Explore Advanced Verilog Concepts.
- Implement Communication Protocols
Program Outcomes
- Ability to design and simulate combinational and
sequential circuits using Verilog. - Understanding of FSMs, timing control, and advanced
Verilog constructs. - Capability to verify and optimize Verilog designs for FPGA
and ASIC implementations. - Industry-Oriented Skillset – Practical expertise in hardware
communication protocols and real-world digital applications.
Pre-requisites
- Knowledge of Digital
Electronics & Logic Design - Familiarity withHDL
languages
(Verilog/VHDL)
Platforms Required
- Xilinx Vivado
- EDA Playground
Topics:
- Designing Methodologies (Top-Down,
Bottom-Up) - Verilog Fundamentals
- Verilog Data Types
- Operators
- Introduction to Gate-Level, Dataflow,
and Behavioral Modeling
Topics:
- Gate Instantiation
- Designing RTL from a Logic Diagram
- Logic Gate Primitives
- Delays in Gate-Level Design
Hands-on:
- Implementing basic logic circuits using GateLevel Modeling
Topics:
Data Flow Modelimg
- Continuous Assignment Statements
- Delays in Dataflow Design
Behavioural Modeling
- Always & Procedural Statements
- Blocking vs. Non-Blocking
Assignments
Timing Control Statements
- Delay-Based Timing Control
- Event-Based Timing Control
Hands-on:
- Writing simple dataflow-based circuits
Topics:
Conditional Statements
- If-Else
- Case (casex, casez)
Looping Constructs
- While, Do While
- For, For Each
- Forever, Repeat
Block Statements
- Sequential Block
- Parallel Block
Hands-On:
- Implementing decision-making and
looping structures in Verilog
Topics:
Finite State Machines (FSMs)
- Mealy Machine
- Moore Machine
Sequential Circuits
- Flip-Flops (D, T, JK, SR)
- Counters (Up, Down, Mod,
Johnson, Ring) - Shift Registers
Hands-On:
- Implementing FSMs, counters, and shift
registers in Verilog
Topics:
- CRC Checking
- Frequency Dividers
- Memory Designs
- PWM (Pulse Width Modulation)
Hands-On:
- Creating a memory module
- Implementing a CRC checker
- Generating PWM signals
Part 1: UART Protocol and SPI (10 Hours)
Topics:
UART Protocol
- UART Protocol
- Serial communication fundamentals
- Verilog implementation of UART
- Transmitter and receiver modeling
- Baud rate generation
SPI (Serial Peripheral Interface)
- Synchronous communication principles
- Master-Slave communication
- SPI Verilog implementation
Part 2: I2C and AXI4 Protocols (10 Hours)
Topics:
I2C (Inter-Integrated Circuit)
- Multi-master, multi-slave communication
- Start/Stop conditions, data transfer
- I2C Verilog implementation
AXI4 (Advanced Extensible Interface 4)
- AXI4 basics and use cases
- Read/write transactions
- Verilog AXI4 interface implementation
Hands-on:
- Developing a UART-based serial
communication system - Implementing an SPI/I2C-based
peripheral communication system - AXI4 interface implementation for highspeed data transfer
Topics:
- Best Practices for RTL Coding
- Optimization of Verilog Code
- Debugging and Verification Strategies
- FPGA Implementation Considerations
Hands-on:
- Final Mini-Project: Design and implement
a complete digital system using Verilog
