Mastering VLSI Design & Verification
Duration: 120 Hrs
Level 1 – 60 Hrs
Level 2 – 60 Hrs
Program Objective :
To equip learners with industry-relevant technical skills and enhance their job readiness through project-based learning, hands-on tool exposure, and real-world application deployment, thereby preparing them for successful employment in core domain areas
Program Outcomes:
- Apply gate, dataflow, and behavioral modeling to develop synthesizable RTL modules.
- Implement FSM-based control logic using Moore or Mealy machine design principles.
- Develop verification environments using System Verilog constructs (e.g., arrays, classes, assertions).
- Gain hands-on experience in designing, simulating, and verifying a real-world digital component.
- Understand functional coverage planning, testbench development, and assertion-based verification, preparing for roles in ASIC/FPGA verification.
Modules:
Level 1 – VLSI Design – 60 Hrs:
Module: RTL Coding with Verilog
- VLSI fundamentals, design methodology
- Different styles of modeling
- Conditional and procedural statements, delay modeling
- Advanced RTL designs
Level 2 – VLSI Verification using System Verilog – 60 Hrs: Module: Design and Verification using System Verilog
- System Verilog concepts, OOP
- Assertions, and
- Complete verification environment design
Experiential Project Based Learning
- A Prototype Digital System Design using RTL Modeling and SystemVerilog-Based Verification
Tools / Platform:
- Xilinx Vivado
- EDA Playground
| Level 1 – VLSI Design (60 Hours) | ||
| Module: RTL Coding with Verilog | ||
| INTRODUCTION TO VLSI: Fundamentals of VLSI | Design Methodology | Verilog data types, Verilog Operators |
| GATE LEVEL MODELING: Gate Instantiate | Design RTL from Logic Diagram, Logic Gate primitive | Delay in Gate level Design |
| DATA FLOW MODELING: Operators in Data Flow | Continuous Assignment (assign statement) | Boolean Equations Representation |
| Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator ?:) | Procedural continuous Assignment Statement |
| Procedural vs Continuous Assignment | Parameterized Data Flow Design | Delay Modeling in Data Flow |
| BEHAVIORAL MODELING: Always, Procedural Statement | Blocking & Non-Blocking Statements | Timing Control: Delay & Event-based |
| If-Else, Case, Casex, Casez | Loops: while, for, forever, repeat | Sequential & Parallel Blocks |
| De-assign, Force, Release Statements | FSM Design (Mealy, Moore), Flip-Flops, Counters, Shift Registers, CRC, PWM | CRC checking, PWM |
| Level 2 – VLSI Verification using System Verilog (60 Hours) | ||
| Module: Design and Verification using System Verilog | ||
| Intro to System Verilog, Need of SV | Verification Environment | Data Types: 2-state, 4-state, enum, string, structure, union, class |
| Arrays: Fixed, Packed, Unpacked | Dynamic, Associative Arrays | Queues |
| Process: Fork-Join, any, none, wait-fork | OOPS: Inheritance, Polymorphism, Encapsulation | Class: Deep/Shallow Copy, Overriding |
| Coverage: Functional, Cross Coverage | Assertions with Examples | Coverage with Examples |
| Explanation of Assertion with Example | Explanation of coverage with examples | Working on Verification Environment |
| Experiential Project Based Learning | ||
| A Prototype Digital System Design using RTL Modeling and SystemVerilog-Based Verification | ||
