Electronic Design Automation (EDA) has undoubtedly changed the design of chips by automating many of the more complex tasks we have to do. However, we are now at the next level with Circuit Foundation Models (CFMs) powered by AI. CFMs are shifting the landscape of circuit design, verification, and optimization, and making chip development faster, smarter, and more efficient.

Key Takeaways

• Circuit Foundation Models use self-supervised learning and fine-tuning to learn the complexity of circuit tasks.
• CFMs provide enhanced accuracy, automation, and efficiency for EDA tasks such as synthesis, verification, and layout.
• AI-native EDA will enable faster design cycles and optimization of power, performance, and area (PPA).
• There are integration issues with CFMs including data quality, explainability, and workflow compatibility.
• Important advances in the future will be multi-modal models and enhanced partnerships between industry and academia.

What Are Circuit Foundation Models?

Circuit Foundation Models are a new generation of AI explicitly designed for EDA and chip design. Unlike conventional artificial intelligence models designed for narrow specific tasks, CFMs are large models that are trained in two parts:

First is self-supervised pre-training—here, the models learn universal behaviors and characteristics by automatically mining enormous volumes of unlabeled circuit data. This phase is critical as it allows the models to learn deeply about circuit structures and behaviors using unlabeled data.

Next is fine-tuning: adapting the model to perform specific tasks such as verifying the correctness of a design or predicting the behavior of a circuit. The two-step process offers CFMs flexibility and usefulness to a myriad of chip design tasks.

CFMs typically come in two main types:

• Encoder models: These are learning a broad representation of circuits and can be used to make predictions about power or timing, for instance.
• Decoder models: These are often based on large language models (LLMs) and can produce outputs such as RTL code or scripted commands that can automate design processes.

By exercising less reliance on large, labeled datasets and more reliance on learning from unwritten circuit data, CFMs can deliver new efficiencies and value add in EDA.

Role of Circuit Foundation Models in EDA

Electronic Design Automation encompasses numerous activities throughout the chip development process: synthesis verification, layout, routing, and more, and CFMs affect these processes in very important ways.

They increase predictive fidelity as they identify design quality problems much earlier in the design process. For example, CFMs can indicate a potential timing violation or power bottleneck prior to embarking on the expensive physical design phase.

Additionally, CFMs generalize well across different types of EDA tasks. Instead of maintaining a collection of isolated tools each intended to tackle a specific narrow task, a single CFM can approach synthesis optimization, verification assertions, or layout recommendations in a manner tuned to that specific phase of the chip design and development process.

One of the biggest benefits is automation. CFMs have the ability to auto-generate verification test scripts or assertions, thereby saving engineers potentially hours of effort because CFMs automate tedious manual tasks. Plus, scripting an entire workflow with artificial intelligence introduces minimal human error and saves substantial turnaround time.

How CFMs Transform Chip Design Processes

Chip design primarily focuses on improving three parameters: power, performance, and area—often referred to as PPA. CFMs allow designers to achieve even better PPA metrics through: (i) Faster design cycles because AI-native EDA tools significantly reduce the simulation and verification steps, (ii) Better optimization as CFMs build knowledge of managing their poorly -defined and conflicting goal of minimizing power while not degrading performances, and (iii) more reliable functional correctness since CFMs can leverage smarter error detection during verification.

For example, a CFM can work alongside the designers and examine a partially completed design and then suggest optimized RTL or reasonable layout modifications to improve the overall chip’s effort to deliver.

If we think in terms of innovation, CFMs can operate on the development versions of code to rapidly code RTL design, or adapt design flows to its designs, which represents a fundamental shift from traditional rule-based EDA.

Why CFMs Matter for Chip Designers

Chip designers consistently endure strict deadlines, heavy complexity, and perpetual pressure to accelerate all efforts while improving yield rates. CFMs can deliver many smart assistant-like capabilities, which can benefit designers in several different ways:

• Allowing designers to receive early warnings whenever a design error is made.
• Accelerating repetitive work effort.
• Providing design optimizations based on prior designs learned through deep learning.

Combined, design cycles improve and allow for more opportunity for innovation, because engineers will be able to use extra time to explore new designs and a lot less time doing repetitive work.

Future Directions and Exciting Trends

The use of CFMs in EDA is a burgeoning field with an accelerating trajectory. In theory, researchers have made practical advances in EDA with CFMs since approximately 2022, and these have involved:

Multimodal Learning: Models that simultaneously process circuit code, circuit layouts (or shapes), circuit specifications, and circuit simulation/pre/post-layout results.

Large Language Models (LLMs): The use of powerful generative AI that understands circuit languages and design intent.

Industry Partnerships: Partnerships between semiconductor companies, AI researchers, and EDA tool vendors to rapidly develop specialized AI-native design tools.

We can anticipate new AI-native design paradigms that will not only automate the current task and workflow, but fundamentally change how chips are designed.

Conclusion

Circuit Foundation Models (CFMs) are undoubtedly reshaping the world of Electronic Design Automation and chip design. CFMs are able to leverage the power of AI to provide more fine-tuned, faster, and optimized chip development with regards to power, performance, and area. For engineers and students looking to break into this field, taking a VLSI design course in Bangalore is an enticing option because Bangalore is a technology hub, there will be better access to state-of-the-art resources, and students and engineers will be exposed to the cutting-edge workflows of modern EDA tools like CFMs . From a semiconductor design and development standpoint it will be crucial to understand AI-driven tools and use them effectively in order to remain competitive.