FPGA
- nasscom and Ministry of Electronics and Information Technology initiative
- Official partner with Cranes Varsity
- Certification from IT-ITeS SSC Council
- Government of India Incentive
Duration– 60 Hours
Certificates
Program Objectives
- Understand FPGA Architecture & Design Flow
- Master RTL Design & Digital Circuit Implementation
- Develop Finite State Machines & Debugging Skills
- Apply FPGA for Real-World Applications
Program Outcomes
- Proficiency in FPGA Design & Implementation
- Hands-on Experience with Combinational & Sequential Circuits
- Debugging & Optimization of FPGA Systems
- Ability to Develop Industry-Ready FPGA Projects
Pre-requisites
- Knowledge of Digital
Electronics & Logic Design
- Familiarity withHDL
languages
(Verilog/VHDL)
Platforms Required
- Xilinx Vivado
- EDA Playground
Hardware Tools Required
Arty-7 / ZYNQ SoC FPGA BoardTopics:
Introduction to FPGA & CPLD
- FPGA vs. CPLD
- FPGA Applications
FPGA Architecture
- Configurable Logic Blocks (CLBs)
- I/O Blocks
- Interconnects
FPGA Working Principle
- Configurable Logic &
Interconnections - Clocking & Power Distribution
Hands-on:
- Overview of FPGA development tools
- Basic setup and design flow in FPGA
Topics:
FPGA Design Flow
- Design Entry (HDL)
- Synthesis
- Place & Route
- Bitstream Generation
- Programming the FPGA
Understanding FPGA Developement Tools
- Vivado, Quartus, Libero, etc.
Basic FPGA Examples
Adders, Subtractors, Counters
Hands-on:
- Implementing Adder/Subtractor on FPGA
- Simulation and debugging techniques
Topics:
Combinational Circuits Implementation
- Multiplexers (MUX) &
Demultiplexers (DEMUX) - Encoders & Decoders
- Arithmetic Circuits
Logic Optimization Techniques
Hands-on:
- Implementing Multiplexers, Encoders, and
Decoders on FPGA - Optimization of combinational logic
Topics:
Flip- Flops Implementation
- D Flip-Flop
- T Flip-Flop
- JK & SR Flip-Flops
Counter Design on FPGA
- Up Counter, Down Counter
- Up-Down Counter
- Mod Counter
- Johnson & Ring Counters
Hands-On:
- Designing and simulating Flip-Flops on FPGA
- Implementing various counters in FPGA
Topics:
Shift Registers
- Serial-In-Serial-Out (SISO)
- Serial-In-Parallel-Out (SIPO)
- Parallel-In-Serial-Out (PISO)
- Parallel-In-Parallel-Out (PIPO)
FSM Design Implementation
- Mealy Machine
- Moore Machine
Introduction to FPGA Debugging Tools
- VIO (Virtual Input/Output)
- ILA (Integrated Logic Analyzer)
Hands-On:
- Implementing Shift Registers
- Designing an FSM-based traffic light controller
Part 1: Project Definition & Design (10 Hours)
Complete FPGA Project Implementation
- Specification & Design
- Coding & Simulation
- Debugging & Optimization
Testing & Deployment on FPGA Hardware
Hands-On:
- Developing a project proposal
- Designing and simulating a complex FPGA-based
system
Part 2: Advanced Real-World Applications (10 Hours)
Application-Specific FPGA Implementations
- High-speed data processing
- Signal processing applications
- Communication system design
Final Demonstration & Evaluation
- Testing FPGA systems under different
conditions - Performance tuning & optimizations
Hands-On:
- Implementing an FPGA-based real-time
digital system - Demonstration of the final project
