Digital Circuit Design using Verilog
Duration – 10 Days-SDP
Objectives
- Learn basics of VLSI and Verilog HDL
- Model digital circuits using gate-level, dataflow, and behavioral styles
- Write and simulate Verilog code
- Design combinational and sequential circuits
Tools & Platforms
- ModelSim / Vivado / QuestaSim
- Verilog HDL
- Windows/Linux systems
Pre-requisites
- Basics of digital electronics (gates, flip-flops)
- Familiarity with logic circuits
- Programming basics (helpful, not mandatory
Take away
- Ability to write and test Verilog code
- Understand modeling techniques
- Build real-time digital designs
- Hands-on experience with delay, timing, CRC, and PWM
Day 2: Data Flow & Advanced Data Flow Modeling
- Operators in Data Flow,
- Continuous Assignment (assign statement),
- Boolean Equations Representation
- Gate-level Abstraction using Data Flow,
- Conditional Assignment (Ternary Operator?)
- Procedural continuous Assignment Statement
- Procedural vs Continuous Assignment,
- Parameterized Data Flow Design,
- Delay Modeling in Data Flow
Day 3: BEHAVIORAL MODELING:
- Structured procedural Statement
- Always Statement, Procedural Statement,
- Blocking Statement,
- Non-Blocking statement,
Day 4: Timing Control Statement:
- Delay based timing control
- Event Based timing control
Day 5: Conditional Statements & Procedural Constructs
- If else statement,
- case statement: casex, casez ,
- Loop: While, do while, for, for each, forever, repeat.
- Block statement, Sequential block, Parallel Block
- De-assign Statement,
- force statement,
- Release statement.
Day 6: Sequential Circuits
- Flip-Flops (D, T, JK, SR)
- Counters (Up, Down, Up-Down)
- Shift Registers (SIPO, PISO, SISO, PIPO)
Day 7: Combinational Circuit
- Design of Combinational Circuits using Verilog
- Importance of Choosing the Right Modeling Technique
Day 8: Delay Control in Verilog
- Delay Control Statements Overview
- Intra Assignment Delay
- Inter Assignment Delay
- Rise, Fall, and Turn-Off Delays
Day 9 & 10: Projects
- Digital Clock with Alarm & Timer – A real-time clock system using FSMs, counters, and behavioral modeling in Verilog.
- UART with CRC Error Detection – A serial communication module with integrated CRC for reliable data transfer.
