Design Verification using SystemVerilog
Duration: 4 Weeks
Project Training – Offline / Online
Program Summary:
- Covers System Verilog concepts and verification methodologies.
- Includes testbench architecture, assertions, and coverage.
- Hands-on labs from RTL to complete testbenches.
- Introduces UVM and functional verification strategies.
- Final project on protocol/interface verification using SV
Program Outcomes:
- Write synthesizable System Verilog and testbenches.
- Apply constrained randomization and assertions (SVA).
- Measure and analyze functional coverage.
- Design modular verification environments (with drivers/monitors).
- Execute and debug real-world verification projects
Project stream:
- Protocol Verification: UART, SPI, I²C, and AXI4 interface validation using SystemVerilog testbenches.
- IP Core Verification: ALU, FIFO, Memory Controller, and CRC checker functional verification.
- FSM-Based Projects: Verification of Traffic Light, Vending Machine, and Elevator control FSMs
Platforms/Tools:
- EDA Playground/ Questasim
- Xilinx Vivado
| Days 1–15: SystemVerilog for Functional Verification | ||
| Day | Topics | Lab Activities / Outcome |
|---|---|---|
| Day 1 | Recap of Verilog & RTL Design Flow | RTL modules: counter, mux |
| Day 2 | Introduction to SystemVerilog | Data types, logic, arrays, typedef |
| Day 3 | Procedural Blocks in SV | always_comb, always_ff, initial, tasks |
| Day 4 | Interfaces and Modports | Create interface for DUT communication |
| Day 5 | SystemVerilog Testbenches | Basic testbench structure |
| Day 6 | Constrained Randomization | rand, randc, constraint blocks |
| Day 7 | Assertion-Based Verification (SVA) | Immediate & concurrent assertions |
| Day 8 | Functional Coverage | Coverpoints, covergroups, bins |
| Day 9 | Classes & OOP in SV | Class hierarchy, inheritance |
| Day 10 | Transaction-Level Modeling | Create transaction objects |
| Day 11 | Building a Driver & Monitor | Connecting testbench to DUT |
| Day 12 | Scoreboard & Checker Concepts | Self-checking testbenches |
| Day 13 | Introduction to UVM | UVM environment overview |
| Day 14 | Verification Plan & Strategy | Develop plan for test cases |
| Day 15 | Integration Practice | Build complete testbench for UART |
| Days 16–20: Project Work (Functional Verification of a Design) | ||
| Day 16 | Test Plan & Environment Setup | Write verification plan, build interface |
| Day 17 | Transaction, Driver, Monitor | Code and connect testbench |
| Day 18 | Assertions & Coverage Integration | Add SVA + functional coverage |
| Day 19 | Debugging & Simulation | Run tests, observe coverage, fix bugs |
| Day 20 | Final Report & Demo | Present design + verification metrics |
