PG Diploma in VLSI Design & ASIC Verification
100% JOB Assured with Globally Accepted Certificate
Duration: 6 Months
Eligibility: BE, B.Tech, ME, M.Tech
Intermediate
Modules
- Digital Hardware Familiarization
- Digital Electronics, Logical circuit design
- Timing analysis
- Mastering in C & C++
- Master in C Programming
- Mastering OOP using C++
- RTL Coding with Verilog
- Digital circuits design with different modeling styles
- On-Chip Protocols Design
- FPGA Programming
- Digital design innovators: RTL to realization
SPECIALIZATIONS:
- Design and Verification using System Verilog
- OOPs in System Verilog
- Randomization & Constraints
- Functional Coverage
- Test bench development
- Verification using UVM (Universal Verification Methodology)
- On-Chip Protocols Verification
- Python Scripting
- Static Timing Analysis
Project stream:
- Application development based on Data Structure (Eg: Multi Client Chat Application, memory Leak Detection tool kit, E-Commerce cart simulator)
- Design and Simulation of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation and Verification of Digital Controllers, ALU Cores and protocols such as UART, SPI, I2C, AXI4 on FPGA Board.
- SV Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- UVM Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
Platform:
• XILINX VIVADO
• Questasim/EDA Playground
• Artix7 FPGA Board
• ZYNQ SOC Board
• Yosys, Open Timer
| Core Engineering | ||
|---|---|---|
| Digital Hardware Familiarization – 40 hrs. – 10 Days – 2 Weeks | ||
| Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics | Diodes, Rectifiers, Zener & Clamping Circuits | BJTs and MOSFETs (Switching & Amplification) |
| Operational Amplifiers (Op-Amps), Filters, Comparators | Digital Electronics & Logic Design: Number Systems & Boolean Algebra | Logic Gates, Multiplexers, Encoders/Decoders |
| Flip-Flops, Counters, Shift Registers, FSMs | Timing Analysis | |
| Core Programming Fundamentals | ||
| Mastering OOP using C++ & Competitive Problem Solving – 60 hrs. – 15 Days – 3 Weeks | ||
| Master in C Programming: Simple C program structure | Literals, Constants, Variables and Data types | Arrays, Sorting and Searching, Strings |
| Mastering in C++ with OOPs concepts | OOP Concepts: Classes, Objects, Abstraction, Encapsulation | Access Specifiers, This pointer, Constructors, Destructors, Operator Overloading |
| Inheritance, Run time polymorphism, Exception Handling | Lambda Expression, Smart Pointers, Templates, STL | Problem Solving using HackerRank |
| VLSI Design | ||
| RTL Coding with Verilog – 60 hrs. – 15 Days – 3 Weeks | ||
| Introduction to VLSI: Fundamentals, Design Methodology | Verilog Data Types, Operators | Gate-Level Modeling: Instantiation, Logic Diagram, Delay Modeling |
| Data Flow Modeling: Continuous Assignment, Boolean Equations, Conditional & Parameterized Data Flow | Behavioral Modeling: Always Blocks, Blocking & Non-Blocking Statements | FSMs (Mealy, Moore), Flip-Flops, Counters, Shift Registers, CRC Checking, PWM |
| On-Chip Protocols Design – 20 hrs. – 5 Days – 1 Week | ||
| UART (Universal Asynchronous Receiver Transmitter) | SPI (Serial Peripheral Interface) | I2C, AXI4 Protocols |
| FPGA Programming – 40 hrs. – 10 Days – 2 Weeks | ||
| Introduction to FPGA, Architecture (CLB, I/O Blocks, Interconnects) | FPGA Design Flow, Tool Usage | Implementations: Adders, Counters, Shift Registers, FSMs (Mealy & Moore) |
| Designing with VIO & ILA | Project: Digital Design Innovators – RTL to Realization | |
| Specializations | ||
| VLSI Verification using System Verilog – 100 hrs. – 25 Days – 5 Weeks | ||
| Introduction to System Verilog, Verification Environment | Data Types: 2-State, 4-State, Enum, String, Structure, Union, Class | Arrays: Fixed, Dynamic, Associative, Queues, Fork-Join Processes |
| OOPs: Inheritance, Polymorphism, Encapsulation | Coverage: Functional & Cross Coverage | Assertions & Verification Environment Implementation |
| ASIC Verification using UVM – 60 hrs. – 15 Days – 3 Weeks | ||
| Introduction to UVM, Base Classes, Phases | Config DB, Reporting Mechanism, TLM Ports | Analysis, FIFO, Callbacks, Test Bench Components |
| On-Chip Protocols Verification – 20 hrs. – 5 Days – 1 Week | ||
| UART (Universal Asynchronous Receiver Transmitter) | SPI (Serial Peripheral Interface) | I2C, AXI4 Protocols |
| Python Scripting – 40 hrs. – 10 Days – 2 Weeks | ||
| Python Fundamentals for Engineers | Data Structures, File Handling, Regular Expressions | EDA Automation, Parsing Reports, Visualization, Verification |
| Timing Verification – 40 hrs. – 10 Days – 2 Weeks | ||
| Static Timing Analysis, RTL Linting, CDC | RTL Synthesis Flow, Clocking & Synchronization | Timing Constraints, Submicron Process, Technology Libraries |
Testimonials
Positive: Communication, Professionalism, Quality, Value I Joined Cranes Varsity without any basic knowledge of programming or any interview-related knowledge. I enhanced my knowledge and skills by joining VLSI Course at Cranes Varsity. I got placed in Onward technologies during the 3rd month of my training as promised by the Cranes Varsity.
I am Nanditha N, have completed B.E. in the field of ECE in 2019, and had a wish to join the core company in the field of VLSI design, then I found Cranes Varsity as the best VLSI Training Institute for my dream to come true, a very best place and I got placed in Insemi Technology. I am very thankful for all the trainers who guided me with the best knowledge and skills and even the placement department who placed me in a very good company and for their great support. I suggest Cranes Varsity as the best training place to gain knowledge that helps us to build our careers.
I am Dileep Kumar T, completed my M.Tech in the stream of VLSI from Dr. AIT, Bangalore in 2019. I joined Cranes Varsity and did my professional course in VLSI Design which includes Verilog, system Verilog, FPGA, and uvm. I had a very good experience with Cranes Varsity, I got multiple opportunities from CranesVaristy. Finally, I got placed in DELOPT as a VLSI Design Engineer
I joined Cranes Varsity for VLSI Design & Verification Course. It is a very good training institute, they placed me in Radiant Semiconductor Pvt Ltd. Trainers were highly skilled and very supportive.
I am Veena Jogannavar, who completed a B.E in the field of ECE in 2020 from Sri Siddhartha Institute of Technology.I came to know about Cranes from my friend. I have undergone VLSI front-end design training and gained good knowledge in Digital electronics, Verilog, and System Verilog. I thank Cranes for providing opportunities for my career growth. At last, I got placed in DELOPT, Bangalore
I am Manavi BR.I have done my M.Tech in VLSI Course and Embedded system from BIT. My dream was to get place in a good core company. Cranes is a good place to learn programming and embedded systems. I got placed in Trident Infosol .I am very thankful to Cranes varsity
Mithun G
Nanditha N
Dileep Kumar T
Gaurav Pandey
Veena Jogannavar
Manavi BR
