Advanced Diploma in VLSI Design & Verification
Duration – 320 hrs. – (4 hrs./day – 2 hrs./day)
Modules
Core Engineering
- Digital Hardware Familiarization – 40hrs.
- Mastering OOP using C++ & Competitive problem solving – 60 hrs.
- RTL Coding with Verilog – 60 hrs.
- On-Chip Protocols Design – 20 hrs.
- FPGA Programming – 40hrs.
SPECIALIZATIONS
- Design and Verification using System Verilog – 100 hrs.
Experiential Project Based Learning
- A Prototype Digital System Design using RTL Modeling, FPGA Deployment, and System Verilog-Based Verification
Project stream:
Core Programming
- Application development based on Data Structure (Eg: Multi Client Chat Application, memory Leak Detection tool kit, E-Commerce cart simulator)
- Design and Simulation of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation and Verification of Digital Controllers, ALU Cores and protocols such as UART, SPI, I2C, AXI4 on FPGA Board.
- SV Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
Platform:
- XILINX VIVADO
- Questasim/EDA Playground
- Artix7 FPGA Board/ ZYNQ SOC Board
| Core Engineering | |||
|---|---|---|---|
| Digital Hardware Familiarization – 40hrs. – 10 Days – 2Weeks/ 20 Days – 4Weeks | |||
| Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics | Diodes, Rectifiers, Zener & Clamping Circuits | BJTs and MOSFETs (Switching & Amplification) | |
| Operational Amplifiers (Op-Amps) | Filters | Comparators | |
| Digital Electronics & Logic Design: Number Systems & Boolean Algebra | Logic Gates, Multiplexers, Encoders/Decoders | Flip-Flops, Counters, Shift Registers, FSMs | |
| Timing Analysis | Circuit Simulation & Debugging | ||
| Core Programming Fundamentals | |||
| Mastering OOP using C++ & Competitive problem solving – 60 hrs. – 15 Days – 3Weeks/ 30Days – 6Weeks | |||
| Master in C Programming: Simple C program structure | Literals, Constants, Variables and Data types | Arrays | |
| Sorting and searching | Strings | Mastering in C++ with OOPs concepts: Introduction to Object-Oriented Programming | |
| Understanding OOP concepts | Basic input/output: cin, cout, endl | Understanding namespace | |
| Classes | Objects | Abstraction | |
| Encapsulation, Access Specifiers – Private and Protected, This pointer | Constructors and Destructors | Friends and operator overloading | |
| Inheritance | Run time polymorphism | Exception Handling | |
| Lambda Expression | Smart Pointers | Templates | |
| STL | Problem Solving using Hacker rank | ||
| VLSI Design | |||
| RTL Coding with Verilog – 60 hrs. – 15 Days – 3Weeks/ 30Days – 6Weeks | |||
| INTRODUCTION TO VLSI: Fundamentals of VLSI, Design Methodology | Verilog data types, Verilog Operators | GATE LEVEL MODELING: Gate Instantiate Design, RTL From logic Diagram, Logic Gate primitive | |
| Delay in Gate level Design | DATA FLOW MODELING: Operators in Data Flow | Continuous Assignment (assign statement) | |
| Boolean Equations Representation | Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator? 🙂 | |
| Procedural continuous Assignment Statement | Procedural vs Continuous Assignment | Parameterized Data Flow Design | |
| Delay Modeling in Data Flow | Case Studies / Examples (ALU, Adders, MUX, Encoders) | ||
| BEHAVIORAL MODELING: Structured procedural Statement: Always Statement, Procedural Statement | Blocking Statement, Non-Blocking statement | Timing Control Statement: Delay based timing control; Event Based timing control | |
| Conditional Statement: If else statement, case statement: casex, casez | Loop: While, do while, for, for each, forever, repeat. | Block statement, Sequential block, Parallel Block | |
| De-assign Statement, force statement, Release statement | |||
| DESIGN OF DIGITAL CIRCUITS FSM: Mealy machine, Moore machine | Flip-flops | Counters, Shift Registers | |
| All combinational and sequential circuits using Verilog | CRC checking, PWM | DESIGN OF DIGITAL CIRCUITS: FSM: Mealy machine, Moore machine | |
| Flip-flops | Counters, Shift Registers | Useful Of Modeling Technique | |
| All combinational and sequential circuit using Verilog | Delay Control Statement: Intra delay, inter delay, rise delay, fall delay | Procedural continuous, Assignment Statement | |
| De-assign Statement, force statement, Release statement | CRC checking, PWM | ||
| On-Chip Protocols Design – 20 hrs. – 5 Days – 1 weeks / 10 Days – 2Weeks | |||
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol | I2C (Inter Integrated Circuit) protocol | |
| AXI4 (Advanced extensible Interface 4) protocol | |||
| FPGA Programming – 40hrs. – 10 Days – 2Weeks/ 20 Days – 4Weeks | |||
| Introduction to FPGA | FPGA Architecture | CLB, I/O blocks, Interconnects | |
| CPLD, FPGA, FPGA Working, Design Flow, Tool Understanding working | Designing basic FPGS example (Adders, Subtractors, Counter) | Implementation of all the combinational circuits on FPGA | |
| Implementation of Flip-flops on FPGA | Implementation of Counters- up counter, down counter, up-down counter, mod- counter, Johnson counter, ring counter | Realization of Shift Registers | |
| Realization of FSM: Mealy machine, Moore machine, Designing with VIO and ILA | Demonstration of a Project on FPGA | ||
| Experiential Project based learning | |||
| Project: Digital design innovators: RTL to realization | |||
| Specializations | |||
| VLSI Verification using System Verilog | |||
| Design and Verification using System Verilog – 100 hrs. – 25 Days – 5 weeks/50 Days – 10Weeks | |||
| Introduction of System Verilog, Need of system Verilog | Environment of Verification | Data types -2satete, 4 state, enum , string, structure, union, class | |
| Array- Fixed array- packed and unpacked array | Dynamic Array, Associative array | Queues | |
| Process: - Fork-join, Fork-join any, Fork-join none, Wait-fork | OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation | Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage. | |
| Explanation of assertion with example | Explanation of coverage with example | Working on verification environment | |
| Experiential Project based learning | |||
| Project: Functional Verification: System Verilog to UVM | |||
