Placement Oriented Diploma Program
Eligibility – B.E, B.TECH, M.E., M.TECH
Duration: 240 Hours
Mode of Training: Offline & Online
Intermediate
Overview
Accelerate Your VLSI Career with Cranes Varsity’s Expert Training
Cranes Varsity’s 240-hour intensive program is designed to equip you with the essential skills to excel in the dynamic world of VLSI design and verification. Whether you’re a budding engineer or a seasoned professional, our comprehensive curriculum, delivered through flexible online and offline modes, provides a solid foundation and advanced expertise.
With over 25 years of industry experience, Cranes Varsity offers a unique blend of theoretical knowledge and practical application. Our expert instructors and state-of-the-art training facilities provide an immersive learning experience. Join us and embark on a journey to a successful career in VLSI design and verification.Core Modules:
- Electronics and Embedded Hardware Fundamentals: Gain a strong grasp of electronic circuits and embedded systems, crucial for understanding VLSI design principles.
- C Programming with MISRA Guidelines: Master C programming, adhering to industry-standard MISRA guidelines to write robust and reliable VLSI code.
- Data Structures and Algorithms: Develop a deep understanding of data structures and algorithms to optimize VLSI designs for performance and efficiency.
- Object-Oriented Programming (OOP) with C++: Learn object-oriented programming concepts using C++ to create modular and reusable VLSI designs.
VLSI Design Specialization:
- RTL Design with Verilog: Dive into the world of RTL design using Verilog, the industry-standard hardware description language.
- FPGA Design and TCL Scripting: Gain practical experience in FPGA design and leverage TCL scripting for efficient design flow automation.
VLSI Verification Specialization:
- SystemVerilog Programming: Master SystemVerilog, a powerful language for advanced verification methodologies, including functional verification and formal verification.Check detailed curriculum below:
The Placement Oriented Program on VLSI Design and Verification at Cranes Varsity is a highly specialized training program that equips students with the skills and knowledge required to excel in the field of VLSI design and verification. With a strong focus on industry relevance and practical training, this program prepares students for successful careers in the VLSI industry.
The curriculum of the program covers a wide range of topics essential to VLSI design and verification, including digital electronics, CMOS circuit design, HDL programming (Verilog and VHDL), Verilog, FPGA, System Verilog , and Universal verification methodologies.
One of the key highlights of the Placement Oriented Program is the strong industry collaboration that Cranes Varsity maintains. The institute has forged partnerships with leading semiconductor companies and VLSI design houses, enabling students to benefit from guest lectures, workshops, and industry visits. This collaboration also provides students with internship opportunities, industry projects, and exposure to the latest trends and advancements in VLSI design and verification.
To enhance students’ employability, the program also focuses on developing essential soft skills, such as communication, teamwork, and problem-solving. Students receive guidance on resume building, interview preparation, and career counseling, ensuring they are well-prepared for job placements. The dedicated placement cell at Cranes Varsity assists students in connecting with industry recruiters and organizing placement drives, maximizing their chances of securing lucrative job offers in top VLSI companies.
By enrolling in the Placement Oriented Program on VLSI Design and Verification, students gain comprehensive knowledge, practical skills, and industry exposure in the field of VLSI. This program prepares them for roles such as VLSI design engineer, verification engineer, ASIC engineer, or FPGA engineer. With a strong emphasis on industry relevance, practical training, and job placement, this program equips students with the necessary tools to succeed in the dynamic and highly competitive VLSI industry.
VLSI Design Course with Placement ensures that a fresher is prepared on the entire essential aspects of the VLSI front end domain, including training on VLSI flow, SOC design, verification concepts, digital design, Verilog, and System Verilog. The VLSI design course content is well structured and mapped with leading industry requirements and their standards.
Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for freshers in finding the right career opportunities. VLSI Design Course ensures that freshers are empowered with all the essential skill sets required for various jobs in the VLSI front end domain. The course is completely practical oriented, with each aspect of the course involving multiple hands-on projects.
VLSI Course Modules
- Foundation to Basic Electronics concepts
- Programming in C and Data Structures
- OOPs with C++14
- Basic Verilog and Advanced Verilog
- FPGA Design Basic and Advanced
- System Verilog
- UVM (Universal Verification Method)
- XILINX
- Modelsim/EDA Playground
- Digital Electronics and Hardware Familiarization
- Software Development Life cycle
- Programming in C following MISRA C
- Linux Commands and Shell Scripting
- ARM CORTEX M4 Programming using Embedded C
- RTL coding with Verilog
- FPGA Design and Basics of TCL Scripting
- VLSI Design of Protocols – UART, I2C, SPI, AXI4
- System Verilog Programming
- UVM (Universal Verification Method)
- Design and Simulation of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation and Verification of Digital Controllers, ALU Cores and protocols such as UART, SPI, I2C , AXI4 on FPGA Board.
- SV Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- UVM Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- XILINX ISE/VIVADO
- Modelsim/EDA Playground
VLSI Design Core Programming
- Analog Electronics: Passive and Active components
- Circuit analysis using KCL and KVL
- Diode, Transistor and Op-amp Circuits
- Digital Electronics: Combinational circuits design: Address, Mux, Encoder, Decoder
- Sequential circuits design: Flipflops, Registers, Counters
- Microprocessors, Microcontrollers,
- Basic Embedded System Architecture
- Standard Interfaces
- Understanding schematics/datasheet
- Fundamentals of Booting for Embedded Processors: Host and Target Development Setups
- Electrostatic Discharge Essentials: Causes of ESD and Prevention of ESD
- Techniques to improve embedded system security
- Introduction to C: Sample C program structure , Literals, constants, variables and data types
- Operators with precedence and associativity
- Control flow statements with Examples
- Constructor and Destructor
- Friends and Operators overloading
- Generic Programming
- Generalization
- Exception Handling
- C++ Library Features
- Inheritance
- Runtime Polymorphism
- Call Back Functions
- Code Optimization and Profiling
VLSI Design Specialization
- Designing Methodology
- Top-Down Methodology
- Bottom-Up Methodology
- Verilog data types
- Verilog Scalar /Vector
- Verilog Arrays
GATE LEVEL MODELING
- Gate Instantiate
- Design RTL From logic Diagram
- Logic Gate primitive
- Delay in Gate Level Design
- Learning about different types of counters, register
- Data Flow modeling
- Continuous Assignment statement
- Synchronous Finite State Machine Design.
BEHAVIORAL MODELING
- Structured procedural Statement: Always Statement, Procedural Statement
- Blocking Statement, Non-Blocking statement
- Timing Control Statement: Delay based timing control, Event Based timing control
- Conditional Statement: If..else statement, case statement: casex, casez
- Loop: While, do while, for, for each, forever, repeat.
- Block statement, Sequential block, Parallel Block
DESIGN OF DIGITAL CIRCUITS
- FSM: Mealy machine, Moore machine
- Flip flop
- Counters, PWM
- Useful Of Modeling Technique
- All combinational and sequential circuit using Verilog
- Delay Control Statement: Intra delay, inter delay, rise delay, fall delay
- Procedural continuous, Assignment Statement
- Design Statement, force statement, Release statement
- CRC checking, UART
- Introduction to FPGA
- FPGA Architecture
- CLB, I/O blocks
- CPLD, FPGA, FPGA Working, Design Flow
- Interconnects, Tool Installation
- working Designing basic FPGS examples (Adder, Subtractor, Counter)
- Design and Implementation of projects on FPAG
- Implementation of Counter – up counter, down counter, up down counter, mod counter, Johnson counter, ring counter
- UART, SPI, I2C, AXI4 on FPGA
- Introduction, Running TCL, Simple Text Output, assigning values to variables, expr,
Compute, Put, - While loop, For and incr, proc, Variable scope – global and upvar, TCL List.
- String Subcommands – length index range, String comparisons
- Associative Arrays, Array – Iterating and use in procedures, Dictionaries, File Access, Information about Files – file, glob
- Invoking Subprocesses from TCL – exec, open, Info.
- Modularization – source, building reusable libraries – packages and namespaces, Creating Commands – eval
- UART: Universal Asynchronous Receiver and Transmitter
- SPI: Serial Peripheral Interface.
- I2C: Inter-Integrated Circuit.,AXI4 protocol
VLSI Verification Specialization
- Introduction of System Verilog, Need of system Verilog
- Environment of Verification
- Data types -2satete, 4 state, enum , string, structure, union, class
- Array- Fixed array- packed and unpacked array
- Dynamic Array, Associative array
- Queues
- Process: – Fork-join, Fork-join any, Fork- join none, Wait-fork
- OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation
- Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage.
- Explanation of assertion with example
- Explanation of coverage with example
- Working on verification environment
Core Programming
- Introduction to C: Simple C program structure, Literals, constants, variables and
data types - Operators with precedence and
associativity - Control flow statements with Examples
- Modular Programming using functions
- Working with multiple files
- Storage Class Specifiers
- Arrays and Strings
- Preprocessor directives
- Pointer
- Dynamic Memory Allocation
- Structures and Bit Fields
- Unons
- Recursion
- Command Line Arguments
- typedef, enumsa
- Conditional Compilation
- Cross Compiler
- Buiding an Executable
- Stratup code, linker script and their use
- Object file and map file
- Coding standards/guidelines for secure and safe coding
- Debugging and Tracing Memory Profiling and analysis
- Introduction to Data Structures
- Stacks and queus
- Linked List
- Stack Implementation using array
- Queue Implementation using array
- Tree: Binay Search Tree
- Code Optimization
- GDB Debugger
- Splint
- G Coverage tool
- G Profiling
- Valgrind software
Project stream:
- Design and Simulation of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation and Verification of Digital Controllers, ALU Cores and protocols suchas UART, SPI, I2C, AXI4 on FPGA Board.
- SV Verification of Digital Controller/CPU Core/Protocols such as UART, SPI, I2C, AXI4
Platform:
- XILINX ISE/VIVADO
- Questasim/EDA Playground
- Spartan 6 FPGA Board
- Artix7 FPGA Board
VLSI Course Content
- Introduction to Embedded System
- Electrostatic Discharge Essentials
- Fundamentals of Booting for Embedded Processors
- Securing Embedded Systems
- SDLC – Development Life cycles and Frameworks
- Agile – an iterative and responsive software development methodology
- Development Bible
- Development and Operations
- Embedded Testing
- IoT Security
- Introduction to C
- Data types and Operators
- Conditional Statements
- Loop Control Structures Modular Programming using Functions
- Storage Classes
- Working with Multiple Files
- Preprocessor
- Conditional Inclusion
- Arrays
- Strings
- GDB Debugger
- Linux Commands & Shell Scripting – 08 hrs
- Introduction to the operating system
- Text Editors: Vim and gedit
- Finding Linux Documentation
- System Navigation command
- Manipulating Data
- Process Related commands Filtering
- Shell scripting Input and output
- Arithmetic Expression
- Decision making Looping Constructs
- LPC/ARM Cortex M3 Programming using Embedded C – 12 hrs
- Introduction to ARM Processor
- GPIO- General Purpose Input Output
- LCD programming
- ADC Programming
- Timers Counters
- Basic Python Programming – 20 hrs
- Introduction to Python
- Python Data types and Conditions
- Control Statements
- Python Functions
- Default arguments
- Functions with variable number of args
- Scope of Variables
- Global Specifier
- Working with multiple files
- List and Tuple
- List Methods
- List Comprehension
- Map and filter functions String
- Set and Dictionary
- Designing Methodology
- Top-Down Methodology
- Bottom-Up Methodology
- Verilog data types
- Verilog Scalar /Vector
- Verilog Arrays
- GATE LEVEL MODELING
- Gate Instantiate
- Design RTL From logic Diagram
- Logic Gate primitive
- Delay in Gate level Design
- Learning about different types of counters, register
- Data Flow modeling
- Continuous Assignment statement
- Synchronous Finite State Machine Design.
- BEHAVIORAL MODELING
- Structured procedural Statement: Always Statement, Procedural Statement
- Blocking Statement, Non-Blocking statement
- Timing Control Statement: Delay based timing control,
- Event Based timing control
- Conditional Statement: If..else statement, case statement: casex, casez
- Loop: While, do while, for, for each, forever, repeat.
- Block statement, Sequential block,
- Parallel Block
- DESIGN OF DIGITAL DEVICES
- FSM: Mealy machine, Moore machine
- Flip flop
- Counters, PWM
- Useful Of Modeling Technique
- All combinational and sequential circuit using Verilog
- Delay Control Statement: Intra delay, inter delay, rise delay, fall delay
- Procedural continuous, Assignment Statement
- Deassign Statement, force statement, Release statement
- CRC checking, UART
- Prototyping using FPGA & SOC FPGA,TCL Scripting – 16 hrs
- Introduction to FPGA
- FPGA Architecture
- CLB, I/O blocks
- CPLD, FPGA, FPGA Working, Design Flow
- Interconnects, Tool Installation
- working Designing basic FPGS example (Adder, Subtractor, Counter)
- Design and Implementation of projects on FPAG
- Implementation of Counter – up counter, down counter, up down counter, mod counter, Johnson counter, ring counter
- UART, SPI, I2C, AXI4 on FPGA
- Introduction, Running Tcl, Simple Text Output, assigning values to variables, expr, Compute, Put, While loop, For and incr, proc,
- Variable scope – global and upvar, TCL List
- String Subcommands – length index range
- String comparisons
- Associative Arrays, Array – Iterating and use in procedures, Dictionaries, File Access
- Information about Files – file, glob
- Invoking Subprocesses from Tcl – exec, open, Info.
- Modularization – source, building reusable libraries – packages and namespaces
- Creating Commands – eval
- VLSI Design of Protocols – UART, I2C, SPI, AXI4 – 16 hrs
- UART: Universal Asynchronous Receiver and Transmitter
- SPI: Serial Peripheral Interface.
- I2C: Inter-Integrated Circuit.
- VLSI Verification Specialization
- Introduction of System Verilog, Need of system Verilog Environment of Verification
- Data types -2satete, 4 state, enum , string, structure, union, class
- Array- Fixed array- packed and unpacked array
- Dynamic Array, Associative array
- Queues
- Process: – Fork-join, Fork-join any, Fork-join none, Wait-fork
- OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation
- Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage.
- Explanation of assertion with example
- Explanation of coverage with example
- Working on verification environment
- Verification using UVM – 24 hrs
- Introduction UVM: why UVM
- UVM Objects: Base classes,
- UVM Macros, UVM Base Class Methods
- UVM Phases, UVM Config DB, UVM Reporting Mechanism,
- UVM TLM Ports, Analysis, Fifo, UVM socket concept,
- UVM Callbacks
- UVM test Bench Components and UVM test Benches.
- Verification of Protocol with UVM – UART
- Verification of Protocols with UVM – I2C
- Verification of Protocols with UVM – SPI
- Verification of Protocols with UVM– I2C
Project Development – 4 / 6/ 8 weeks
Phase-1: Research, Planning, and Initial Development
Project Scope Definition
Research & Feasibility Study
Initial Planning & Setup
Project Phase-2: Development, Testing, and Refinement
Development & Iteration
Testing and Validation
Refinement & Optimization
Prepare for Final Deliverables
Final Project Demo and Presentation
Core Programming:
- Introduction to Embedded System
- Electrostatic Discharge Essentials
- Fundamentals of Booting for Embedded Processors
- Securing Embedded Systems
- SDLC – Development Life cycles and Frameworks
- Agile – an iterative and responsive software development methodology
- Development Bible
- Development and Operations
- Embedded Testing
- IoT Security
- Introduction to the operating system
- Text Editors: Vim and gedit
- Finding Linux Documentation
- System Navigation command
- Manipulating Data
- Process Related commands Filtering
- Shell scripting Input and output
- Arithmetic Expression
- Decision making Looping Constructs
- Introduction to ARM Processor
- GPIO- General Purpose Input Output
- LCD programming
- ADC Programming
- Timers
- Counters
- Introduction to Python
- Python Data types and Conditions
- Control Statements
- Python Functions
- Default arguments
- Functions with variable number of args
- Scope of Variables
- Global Specifier
- Working with multiple files
- List and Tuple
- List Methods
- List Comprehension
- Map and filter functions
- String
- Set and Dictionary
- ADC Programming
- Timers
- Counters
VLSI Design Specialization:
- Designing Methodology
- Top-Down Methodology
- Bottom-Up Methodology
- Verilog data types
- Verilog Scalar /Vector
- Verilog Arrays
GATE LEVEL MODELING
- Gate Instantiate
- Design RTL From logic Diagram
- Logic Gate primitive
- Delay in Gate level Design
- Learning about different types of counters, register
- Data Flow modeling
- Continuous Assignment statement
- Synchronous Finite State Machine Design.
BEHAVIORAL MODELING
- Structured procedural Statement: Always Statement, Procedural Statement
- Blocking Statement, Non-Blocking statement
- Timing Control Statement: Delay based timing control, Event Based timing control
- Conditional Statement: If..else statement, case statement: casex, casez
- Loop: While, do while, for, for each, forever, repeat.
Block statement, Sequential block,Parallel Block
DESIGN OF DIGITAL DEVICES
- FSM: Mealy machine, Moore machine
- Flip flop
- Counters, PWM
- Useful Of Modeling Technique
- All combinational and sequential circuit using Verilog
- Delay Control Statement: Intra delay, inter delay, rise delay, fall delay
- Procedural continuous, Assignment Statement
- Deassign Statement, force statement, Release statement
- CRC checking, UART
- Introduction to FPGA
- FPGA Architecture
- CLB, I/O blocks
- CPLD, FPGA, FPGA Working, Design Flow
- Interconnects, Tool Installation
- Working Designing basic FPGS example (Adder, Subtractor, Counter)
- Design and Implementation of projects on FPAG
- Implementation of Counter – up counter, down counter, up down counter, mod counter, Johnson counter, ring counter
- UART, SPI, I2C, AXI4 on FPGA
- Introduction, Running Tcl, Simple Text Output, assigning values to variables, expr, Compute, Put,
- While loop, For and incr, proc, Variable scope – global and upvar, TCL List.
- String Subcommands – length index range, String comparisons
- Associative Arrays, Array – Iterating and use in procedures, Dictionaries, File Access, Information about Files – file, glob
- Invoking Subprocesses from Tcl – exec, open, Info.
- Modularization – source, building reusable libraries – packages and namespaces, Creating Commands – eval
- UART: Universal Asynchronous Receiver and Transmitter
- SPI: Serial Peripheral Interface.
- I2C: Inter-Integrated Circuit.
VLSI Verification Specialization:
- Introduction of System Verilog, Need of system Verilog
- Environment of Verification
- Data types -2satete, 4 state, enum , string, structure, union, class
- Array- Fixed array- packed and unpacked array
- Dynamic Array, Associative array
- Queues
- Process: – Fork-join, Fork-join any, Fork-join none, Wait-fork
- OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation
- Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage.
- Explanation of assertion with example
- Explanation of coverage with example
- Working on verification environment
- Introduction UVM: why UVM
- UVM Objects: Base classes,
- UVM Macros, UVM Base Class Methods
- UVM Phases, UVM Config DB, UVM Reporting Mechanism,
- UVM TLM Ports, Analysis, Fifo, UVM socket concept, UVM Callbacks
- UVM test Bench Components and UVM test Benches.
- Verification of Protocol with UVM – UART
- Verification of Protocols with UVM – I2C
- Verification of Protocols with UVM – SPI
- Verification of Protocols with UVM– I2C
Hiring Partners
FAQs
What is a Placement Eligibility test?
One should clear the pre-placement process which includes Aptitude tests, Placement tests, and Technical and HR Practice Tests Interviews. Clearing these tests is mandatory for anyone to get into placements.
Can I get 100% guaranteed placements by joining VLSI Course Online?
Our Principle- “We assist until we place”. Cranes Varsity shoulders the responsibility of placing its students. So anyone who is joining the course at Cranes Varsity is provided with assured placements.
Do I have to pay extra for course material & placements?
No. Once a student is enrolled in the program, he will get access to our Student Portal which will have study material and interview questions. Cranes Varsity has ATPC – Admission, Training, Placement, and Certificate – Approach. There are no additional charges involved.
If any student wants to have a hard copy of course material then they may have to bear a nominal charge which is not a part of the regular course fee.
