VHDL for SOC - FPGA Design
- nasscom and Ministry of Electronics and Information Technology initiative
- Official partner with Cranes Varsity
- Certification from IT-ITeS SSC Council
- Government of India Incentive
Duration– 50 Hours
Certificates
Program Objectives
• To learn essentials of FPGA
• To simulate and synthesize various RTL designs
• Understand SoC design
• Hands on HDL coding and simulation using Xilinx ISE/VIVADO
• Soft/Hard Processor Design
Pre-requisites
- Participants are required to have basic knowledge on the following topics:
-Digital design theory basics.
-HDL Programming
Platforms Required
– Xilinx Vivado/EDA playground
– ARTIX FPGA/Spartan 6
Essentials of FPGA :
• Introduction to FPGA
• FPGA basic Architecture
• FPGA Internal resource
• FPGA Design Essentials
• FPGA Input/output Blocks (IOBs)
• Special FPGA functions.
• Logic synthesis
VHDL Basics Review
• The shape of VHDL
• Demo: Multiplexer
• Data Types
• Concurrent Operations
• Processes and Variables
• Different types of VHDL Design
• Designing Combinational Circuits
• Designing Sequential Circuits
• Introduction to Testbenches
• Creating memory (RAM/ROM)
• FIFO Designs
• FSM Design
• Functions
• Coding State Machines
• Writing a good test bench
• Synthesis vs simulation
• Writing synthesisable VHDL Code
• Best Practise for RTL design
• Designing with IP
SoC Design Modules
• What is SoC Design
• Need for SoC
• Soc Design flow using soft and hard processor
• Introduction to Zynq SoC
• Hands on FPGA Board
• Xilinx VIVADO
• Tool Flow basics and Understanding
• IP FLOW
• Software Development Design with C
• Timing Analysis
• Applying constraints and viewing reports
• IO pin planning
• Clock Constraints
• Reset Constraints
• FPGA Resources for DSP application
• Hands on FPGA Board
Soft/hard Processor Design
• FPGA Resources for DSP application
• Hands on FPGA Board
• Programmable Logic(PL) Implementation example
• Processor System Implementation example
• PS-PL Implementation example.
